From 24bf68e381ecfa73b72e5ccfb7bceb791b10e0d7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 15 May 2026 15:25:40 +0100 Subject: [PATCH] target/arm/ptw: Flip sense of get_phys_addr_for_at return value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20260515142541.571911-14-peter.maydell@linaro.org --- target/arm/internals.h | 2 ++ target/arm/ptw.c | 2 +- target/arm/tcg/cpregs-at.c | 12 ++++++------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 00830b1724..139c8d1769 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1526,6 +1526,8 @@ bool get_phys_addr(CPUARMState *env, vaddr address, * * Similar to get_phys_addr, but for use by AccessType_AT, i.e. * system instructions for address translation. + * + * Returns: false on translation failure, true on success. */ bool get_phys_addr_for_at(CPUARMState *env, vaddr address, unsigned prot_check, ARMMMUIdx mmu_idx, ARMSecuritySpace space, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8cfa22fb69..d1f23340aa 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3851,7 +3851,7 @@ bool get_phys_addr_for_at(CPUARMState *env, vaddr address, * check is handled or bypassed by .in_prot_check) and "memop = MO_8" * bypasses any alignment check. */ - return !get_phys_addr_nogpc(env, &ptw, address, + return get_phys_addr_nogpc(env, &ptw, address, MMU_DATA_LOAD, MO_8, result, fi); } diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 53dd67375d..1c819c1cdb 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -31,17 +31,17 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, bool format64 = false; ARMMMUFaultInfo fi = {}; GetPhysAddrResult res = {}; - bool ret = get_phys_addr_for_at(env, value, prot_check, - mmu_idx, ss, &res, &fi); + bool ok = get_phys_addr_for_at(env, value, prot_check, + mmu_idx, ss, &res, &fi); /* * ATS operations only do S1 or S1+S2 translations, so we never * have to deal with the ARMCacheAttrs format for S2 only. * (Note that res fields are only valid on ptw success.) */ - assert(ret || !res.cacheattrs.is_s2_format); + assert(!ok || !res.cacheattrs.is_s2_format); - if (ret) { + if (!ok) { /* * Some kinds of translation fault must cause exceptions rather * than being reported in the PAR. @@ -144,7 +144,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, if (format64) { /* Create a 64-bit PAR */ par64 = (1 << 11); /* LPAE bit always set */ - if (!ret) { + if (ok) { par64 |= res.f.phys_addr & ~0xfffULL; if (!res.f.attrs.secure) { par64 |= (1 << 9); /* NS */ @@ -169,7 +169,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * translation table format (with WnR always clear). * Convert it to a 32-bit PAR. */ - if (!ret) { + if (ok) { /* We do not set any attribute bits in the PAR */ if (res.f.lg_page_size == 24 && arm_feature(env, ARM_FEATURE_V7)) {