From 394c4db5cfe52cb3f6f0f6b4af3dd365527d14f3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 May 2026 15:02:08 -0700 Subject: [PATCH] target/arm: Update SCR bits for Arm ARM M.a.a Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260522220306.235200-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15a13b9292..3c2bf476b2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1820,6 +1820,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_AIEN (1ULL << 46) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) +#define SCR_ENFPM (1ULL << 50) +#define SCR_TMEA (1ULL << 51) +#define SCR_TWERR (1ULL << 52) +#define SCR_PFAREN (1ULL << 53) +#define SCR_SRMASKEN (1ULL << 54) +#define SCR_ENIDCP128 (1ULL << 55) +#define SCR_DSE (1ULL << 57) +#define SCR_ENDSE (1ULL << 58) +#define SCR_FGTEN2 (1ULL << 59) +#define SCR_HDBSSEN (1ULL << 60) +#define SCR_HACDBSEN (1ULL << 61) #define SCR_NSE (1ULL << 62) /* GCSCR_ELx fields */