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hw/ppc/pegasos2: Add VOF support for pegasos1
When running without firmware ROM using Virtual Open Firmware we need to do some hardware initialisation and provide the device tree as the machine firmware would normally do. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/d2d7f173dbd436b47382f384d5a93eb7e713424e.1761176219.git.balaton@eik.bme.hu Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
This commit is contained in:
BALATON Zoltan
committed by
Harsh Prateek Bora
Harsh Prateek Bora
parent
d3a16439c3
commit
3c21f9dfcf
@@ -1652,6 +1652,7 @@ F: hw/ppc/pegasos2.c
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F: hw/pci-host/mv64361.c
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F: hw/pci-host/mv643xx.h
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F: include/hw/pci-host/mv64361.h
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F: pc-bios/dtb/pegasos[12].dt[sb]
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amigaone
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M: BALATON Zoltan <balaton@eik.bme.hu>
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@@ -84,6 +84,7 @@ struct PegasosMachineState {
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uint64_t initrd_size;
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};
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static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size);
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static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size);
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static void pegasos_cpu_reset(void *opaque)
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@@ -314,6 +315,82 @@ static void pegasos_init(MachineState *machine)
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}
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}
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static void pegasos_superio_write(uint8_t addr, uint8_t val)
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{
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cpu_physical_memory_write(0xfe0003f0, &addr, 1);
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cpu_physical_memory_write(0xfe0003f1, &val, 1);
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}
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static void pegasos1_pci_config_write(PegasosMachineState *pm, int bus,
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uint32_t addr, uint32_t len, uint32_t val)
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{
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addr |= BIT(31);
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cpu_physical_memory_write(0xfec00cf8, &addr, 4);
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cpu_physical_memory_write(0xfee00cfc, &val, len);
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}
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static void pegasos1_chipset_reset(PegasosMachineState *pm)
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{
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uint8_t elcr = 0x2e;
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cpu_physical_memory_write(0xfe0004d1, &elcr, sizeof(elcr));
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pegasos1_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x50, 1, 0x6);
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pegasos_superio_write(0xf4, 0xbe);
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pegasos_superio_write(0xf6, 0xef);
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pegasos_superio_write(0xf7, 0xfc);
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pegasos_superio_write(0xf2, 0x14);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x51, 1, 0x3d);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x55, 1, 0x90);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x56, 1, 0x99);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 0) << 8) |
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0x57, 1, 0x90);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x10e);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_CLASS_PROG, 1, 0xf);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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0x40, 1, 0xb);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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0x50, 4, 0x17171717);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 1) << 8) |
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PCI_COMMAND, 2, 0x87);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 2) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x409);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 3) << 8) |
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PCI_COMMAND, 2, 0x7);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x48, 4, 0x2001);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x41, 1, 0);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 4) << 8) |
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0x90, 4, 0x1000);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 5) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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pegasos1_pci_config_write(pm, 0, (PCI_DEVFN(7, 6) << 8) |
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PCI_INTERRUPT_LINE, 2, 0x309);
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}
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static uint32_t pegasos2_mv_reg_read(PegasosMachineState *pm,
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uint32_t addr, uint32_t len)
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{
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@@ -357,12 +434,6 @@ static void pegasos2_pci_config_write(PegasosMachineState *pm, int bus,
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pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
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}
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static void pegasos2_superio_write(uint8_t addr, uint8_t val)
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{
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cpu_physical_memory_write(0xfe0003f0, &addr, 1);
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cpu_physical_memory_write(0xfe0003f1, &val, 1);
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}
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static void pegasos2_chipset_reset(PegasosMachineState *pm)
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{
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pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
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@@ -379,10 +450,10 @@ static void pegasos2_chipset_reset(PegasosMachineState *pm)
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PCI_INTERRUPT_LINE, 2, 0x9);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
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0x50, 1, 0x6);
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pegasos2_superio_write(0xf4, 0xbe);
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pegasos2_superio_write(0xf6, 0xef);
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pegasos2_superio_write(0xf7, 0xfc);
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pegasos2_superio_write(0xf2, 0x14);
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pegasos_superio_write(0xf4, 0xbe);
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pegasos_superio_write(0xf6, 0xef);
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pegasos_superio_write(0xf7, 0xfc);
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pegasos_superio_write(0xf2, 0x14);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
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0x50, 1, 0x2);
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pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
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@@ -432,7 +503,7 @@ static void pegasos2_chipset_reset(PegasosMachineState *pm)
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static void pegasos_machine_reset(MachineState *machine, ResetType type)
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{
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PegasosMachineState *pm = PEGASOS_MACHINE(machine);
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void *fdt;
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void *fdt = NULL;
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uint32_t c[2];
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uint64_t d[2];
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int sz;
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@@ -440,13 +511,22 @@ static void pegasos_machine_reset(MachineState *machine, ResetType type)
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qemu_devices_reset(type);
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if (!pm->vof) {
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return; /* Firmware should set up machine so nothing to do */
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} else if (pm->type == PEGASOS1) {
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error_report("VOF is not supported by this machine");
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exit(1);
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}
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/* Otherwise, set up devices that board firmware would normally do */
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pegasos2_chipset_reset(pm);
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switch (pm->type) {
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case PEGASOS1:
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pegasos1_chipset_reset(pm);
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fdt = pegasos1_build_fdt(pm, &sz);
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break;
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case PEGASOS2:
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pegasos2_chipset_reset(pm);
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fdt = pegasos2_build_fdt(pm, &sz);
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break;
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}
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if (!fdt) {
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exit(1);
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}
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/* Device tree and VOF set up */
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vof_init(pm->vof, machine->ram_size, &error_fatal);
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@@ -465,11 +545,6 @@ static void pegasos_machine_reset(MachineState *machine, ResetType type)
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exit(1);
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}
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fdt = pegasos2_build_fdt(pm, &sz);
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if (!fdt) {
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exit(1);
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}
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/* Set memory size */
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c[0] = 0;
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c[1] = cpu_to_be32(machine->ram_size);
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@@ -761,6 +836,8 @@ static struct {
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const char *name;
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void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
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} device_map[] = {
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{ "pci10cc,660", "host", NULL },
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{ "pci10cc,661", "host", NULL },
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{ "pci11ab,6460", "host", NULL },
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{ "pci1106,571", "ide", dt_ide },
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{ "pci1106,3044", "firewire", NULL },
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@@ -846,7 +923,7 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
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qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
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pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
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}
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/* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
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/* Pegasos firmware has subsystem-id and subsystem-vendor-id swapped */
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qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
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pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
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qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
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@@ -934,6 +1011,27 @@ static void *load_dtb(const char *filename, int *fdt_size)
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return fdt;
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}
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static void *pegasos1_build_fdt(PegasosMachineState *pm, int *fdt_size)
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{
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FDTInfo fi;
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PCIBus *pci_bus;
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void *fdt = load_dtb("pegasos1.dtb", fdt_size);
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if (!fdt) {
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return NULL;
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}
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qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos");
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add_cpu_info(fdt, pm->cpu, pm->bus_freq_hz);
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fi.fdt = fdt;
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fi.path = "/pci@80000000";
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pci_bus = PCI_BUS(qdev_get_child_bus(pm->nb, "pci.0"));
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pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
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return fdt;
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}
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static void *pegasos2_build_fdt(PegasosMachineState *pm, int *fdt_size)
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{
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FDTInfo fi;
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@@ -1,6 +1,7 @@
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dtbs = [
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'bamboo.dtb',
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'canyonlands.dtb',
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'pegasos1.dtb',
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'pegasos2.dtb',
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'petalogix-ml605.dtb',
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'petalogix-s3adsp1800.dtb',
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BIN
pc-bios/dtb/pegasos1.dtb
Normal file
BIN
pc-bios/dtb/pegasos1.dtb
Normal file
Binary file not shown.
125
pc-bios/dtb/pegasos1.dts
Normal file
125
pc-bios/dtb/pegasos1.dts
Normal file
@@ -0,0 +1,125 @@
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/*
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* QEMU Pegasos1 Device Tree Source
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*
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* Copyright 2025 BALATON Zoltan
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This is partial source, more info will be filled in by board code.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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device_type = "chrp";
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model = "Pegasos";
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revision = "1A";
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CODEGEN,vendor = "bplan GmbH";
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CODEGEN,board = "Pegasos";
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CODEGEN,description = "Pegasos CHRP PowerPC System";
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openprom {
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model = "Pegasos,0.1b123";
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};
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chosen {
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};
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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#cpus = <1>;
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};
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failsafe {
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device_type = "serial";
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};
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pci@80000000 {
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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clock-frequency = <33333333>;
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8259-interrupt-acknowledge = <0xfef00000>;
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reg = <0x80000000 0x7f000000>;
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ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00800000
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0x02000000 0 0x80000000 0x80000000 0 0x7d000000
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0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>;
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bus-range = <0 0>;
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isa@7 {
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vendor-id = <0x1106>;
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device-id = <0x8231>;
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revision-id = <0x10>;
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class-code = <0x60100>;
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/* Pegasos firmware has subsystem-id and */
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/* subsystem-vendor-id swapped */
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subsystem-id = <0x1af4>;
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subsystem-vendor-id = <0x1100>;
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reg = <0x3800 0 0 0 0>;
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device_type = "isa";
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#address-cells = <2>;
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#size-cells = <1>;
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eisa-slots = <0>;
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clock-frequency = <8333333>;
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slot-names = <0>;
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serial@i2f8 {
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device_type = "serial";
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reg = <1 0x2f8 8>;
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interrupts = <3 0>;
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clock-frequency = <0>;
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};
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8042@i60 {
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device_type = "";
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reg = <1 0x60 5>;
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clock-frequency = <0>;
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interrupt-controller = "";
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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keyboard@i60 {
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device_type = "keyboard";
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reg = <1 0x60 5>;
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interrupts = <1 0>;
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};
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rtc@i70 {
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device_type = "rtc";
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reg = <1 0x70 2>;
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interrupts = <8 0>;
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clock-frequency = <0>;
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compatible = "ds1385-rtc";
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};
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timer@i40 {
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device_type = "timer";
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reg = <1 0x40 8>;
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clock-frequency = <0>;
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};
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fdc@i3f0 {
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device_type = "fdc";
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reg = <1 0x3f0 8>;
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interrupts = <6 0>;
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clock-frequency = <0>;
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};
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lpt@i3bc {
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device_type = "lpt";
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reg = <1 0x3bc 8>;
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interrupts = <7 0>;
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clock-frequency = <0>;
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};
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};
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};
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};
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