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target/riscv: Introduce mo_endian() helper

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mo_endian() returns the target endianness from DisasContext.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251010155045.78220-13-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philippe Mathieu-Daudé
2025-10-10 17:50:43 +02:00
committed by Alistair Francis
parent 6f825fd491
commit 504f7f304f
10 changed files with 39 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
target/riscv/insn_trans/trans_rva.c.inc
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@@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGv src1;
mop |= MO_ALIGN;
mop |= MO_TE;
mop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
src1 = get_address(ctx, a->rs1, 0);
@@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l2 = gen_new_label();
mop |= MO_ALIGN;
mop |= MO_TE;
mop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
src1 = get_address(ctx, a->rs1, 0);

4
target/riscv/insn_trans/trans_rvd.c.inc
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@@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
} else {
memop |= MO_ATOM_IFALIGN;
}
memop |= MO_TE;
memop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
addr = get_address(ctx, a->rs1, a->imm);
@@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
} else {
memop |= MO_ATOM_IFALIGN;
}
memop |= MO_TE;
memop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
addr = get_address(ctx, a->rs1, a->imm);

4
target/riscv/insn_trans/trans_rvf.c.inc
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@@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
memop |= MO_TE;
memop |= mo_endian(ctx);
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
memop |= MO_TE;
memop |= mo_endian(ctx);
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}

4
target/riscv/insn_trans/trans_rvi.c.inc
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@@ -402,7 +402,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
bool out;
memop |= MO_TE;
memop |= mo_endian(ctx);
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@@ -504,7 +504,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
memop |= MO_TE;
memop |= mo_endian(ctx);
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}

4
target/riscv/insn_trans/trans_rvzacas.c.inc
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@@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGv src1 = get_address(ctx, a->rs1, 0);
TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
mop |= MO_TE;
mop |= mo_endian(ctx);
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);
@@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a)
TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE);
MemOp memop = MO_ALIGN | MO_UO;
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_concat_i64_i128(src2, src2l, src2h);
tcg_gen_concat_i64_i128(dest, destl, desth);
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);

4
target/riscv/insn_trans/trans_rvzce.c.inc
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@@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
tcg_gen_addi_tl(addr, sp, stack_adj - reg_size);
memop |= MO_TE;
memop |= mo_endian(ctx);
for (i = X_Sn + 11; i >= 0; i--) {
if (reg_bitmap & (1 << i)) {
TCGv dest = dest_gpr(ctx, i);
@@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a)
tcg_gen_subi_tl(addr, sp, reg_size);
memop |= MO_TE;
memop |= mo_endian(ctx);
for (i = X_Sn + 11; i >= 0; i--) {
if (reg_bitmap & (1 << i)) {
TCGv val = get_gpr(ctx, i, EXT_NONE);

4
target/riscv/insn_trans/trans_rvzfh.c.inc
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@@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
REQUIRE_FPU;
REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
memop |= MO_TE;
memop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
@@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
REQUIRE_FPU;
REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
memop |= MO_TE;
memop |= mo_endian(ctx);
decode_save_opc(ctx, 0);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {

4
target/riscv/insn_trans/trans_rvzicfiss.c.inc
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@@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
src1 = get_address(ctx, a->rs1, 0);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);
gen_set_gpr(ctx, a->rd, dest);
return true;
@@ -135,7 +135,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
src1 = get_address(ctx, a->rs1, 0);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);
gen_set_gpr(ctx, a->rd, dest);
return true;

16
target/riscv/insn_trans/trans_xthead.c.inc
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@@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv_i64 rd = cpu_fpr[a->rd];
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
if ((memop & MO_SIZE) == MO_32) {
gen_nanbox_s(rd, rd);
@@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv_i64 rd = cpu_fpr[a->rd];
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
return true;
@@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
TCGv rd = dest_gpr(ctx, a->rd);
TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rd, rd);
@@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rs1, rs1);
@@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv rd = dest_gpr(ctx, a->rd);
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, rd);
@@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
@@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
addr1 = get_address(ctx, a->rs, imm);
addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);
tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd1, t1);
@@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
addr1 = get_address(ctx, a->rs, imm);
addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
memop |= MO_TE;
memop |= mo_endian(ctx);
tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);
return true;

18
target/riscv/translate.c
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@@ -126,6 +126,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa_ext & ext;
}
static inline MemOp mo_endian(DisasContext *ctx)
{
/*
* A couple of bits in MSTATUS set the endianness:
* - MSTATUS_UBE (User-mode),
* - MSTATUS_SBE (Supervisor-mode),
* - MSTATUS_MBE (Machine-mode)
* but we don't implement that yet.
*/
return MO_TE;
}
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -142,7 +154,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#define get_address_xl(ctx) ((ctx)->address_xl)
#endif
#define mxl_memop(ctx) ((get_xl(ctx) + 1) | MO_TE)
#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx))
/* The word size for this machine mode. */
static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
@@ -1135,7 +1147,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
MemOp size = mop & MO_SIZE;
mop |= MO_TE;
mop |= mo_endian(ctx);
if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
mop |= MO_ATOM_WITHIN16;
} else {
@@ -1156,7 +1168,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGv src1 = get_address(ctx, a->rs1, 0);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
mop |= MO_TE;
mop |= mo_endian(ctx);
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);