From 5e3906dcfaa1427c6f890c85b4fce281dcb16531 Mon Sep 17 00:00:00 2001 From: Jim MacArthur Date: Thu, 2 Apr 2026 15:20:29 +0100 Subject: [PATCH] tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313 These are not formats in themselves, but extra constants to OR in with the existing ldst_imm format. Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260402-aarch64-tcg-instruction-format-rename2-v1-2-0998a08a515c@linaro.org> --- tcg/aarch64/tcg-target.c.inc | 64 ++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 29 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 23d96a7960..cc9c2a5158 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -458,8 +458,9 @@ typedef enum { Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30, Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30, - Ildst_imm_TO_I3310 = 0x00200800, - Ildst_imm_TO_I3313 = 0x01000000, + /* Additions to the ldst_imm format */ + ldst_imm_to_reg = 0x00200800, + ldst_imm_to_uimm = 0x01000000, /* Load/store register pair instructions. */ Ildstpair_LDP = 0x28400000, @@ -880,13 +881,13 @@ static void tcg_out_insn_qrr_e(TCGContext *s, AArch64Insn insn, bool q, | (rn & 0x1f) << 5 | (rd & 0x1f)); } -static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, - TCGReg regoff) +static void tcg_out_insn_ldst_reg(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg base, TCGType ext, + TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); + tcg_out32(s, insn | ldst_imm_to_reg | regoff << 16 | 0x4000 | ext << 13 | + base << 5 | (rd & 0x1f)); } static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn, @@ -895,11 +896,11 @@ static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn, tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); } -static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) +static void tcg_out_insn_ldst_uimm(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10 + tcg_out32(s, insn | ldst_imm_to_uimm | scaled_uimm << 10 | rn << 5 | (rd & 0x1f)); } @@ -1203,9 +1204,6 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, g_assert_not_reached(); } -/* Define something more legible for general use. */ -#define tcg_out_ldst_r tcg_out_insn_3310 - static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, TCGReg rn, intptr_t offset, int lgsize) { @@ -1214,7 +1212,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) { uintptr_t scaled_uimm = offset >> lgsize; if (scaled_uimm <= 0xfff) { - tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); + tcg_out_insn_ldst_uimm(s, insn, rd, rn, scaled_uimm); return; } } @@ -1227,7 +1225,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, /* Worst-case scenario, move offset to temp register, use reg offset. */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); + tcg_out_insn_ldst_reg(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); } static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) @@ -1764,28 +1762,32 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_LDRB, data_r, h.base, + h.index_ext, h.index); break; case MO_SB: - tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW, - data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW, + data_r, h.base, h.index_ext, h.index); break; case MO_UW: - tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, + h.index); break; case MO_SW: - tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW), - data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW, + data_r, h.base, h.index_ext, h.index); break; case MO_UL: - tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, + h.index); break; case MO_SL: - tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext, - h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext, + h.index); break; case MO_UQ: - tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, + h.index); break; default: g_assert_not_reached(); @@ -1797,16 +1799,20 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_STRB, data_r, h.base, + h.index_ext, h.index); break; case MO_16: - tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_STRH, data_r, h.base, + h.index_ext, h.index); break; case MO_32: - tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_STRW, data_r, h.base, + h.index_ext, h.index); break; case MO_64: - tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_reg(s, Ildst_imm_STRX, data_r, h.base, + h.index_ext, h.index); break; default: g_assert_not_reached();