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buildsys: Remove MIPS KVM

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We removed support for MIPS host. The KVM MIPS code
is now unreachable, remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260511135312.38705-5-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2026-05-11 11:19:16 +02:00
parent 689933a7c7
commit 630decdfcc
13 changed files with 21 additions and 1408 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@@ -483,12 +483,6 @@ S: Supported
F: target/arm/kvm.c
F: tests/functional/aarch64/test_kvm.py
MIPS KVM CPUs
M: Huacai Chen <chenhuacai@kernel.org>
S: Odd Fixes
F: target/mips/kvm*
F: target/mips/system/
PPC KVM CPUs
M: Nicholas Piggin <npiggin@gmail.com>
R: Harsh Prateek Bora <harshpb@linux.ibm.com>

2
docs/system/target-mips.rst
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@@ -76,8 +76,6 @@ The Loongson-3 virtual platform emulation supports:
- GPEX and virtio as peripheral devices
- Both KVM and TCG supported
.. include:: cpu-models-mips.rst.inc
.. _nanoMIPS-System-emulator:

11
hw/intc/mips_gic.c
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@@ -15,9 +15,7 @@
#include "qapi/error.h"
#include "hw/core/sysbus.h"
#include "system/memory.h"
#include "system/kvm.h"
#include "system/reset.h"
#include "kvm_mips.h"
#include "hw/intc/mips_gic.h"
#include "hw/core/irq.h"
#include "hw/core/qdev-properties.h"
@@ -45,14 +43,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin)
ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >>
GIC_VP_MASK_CMP_SHF;
}
if (kvm_enabled()) {
kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env),
pin + GIC_CPU_PIN_OFFSET,
ored_level);
} else {
qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
ored_level);
}
qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], ored_level);
}
static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ)

38
hw/mips/loongson3_virt.c
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@@ -45,7 +45,6 @@
#include "hw/pci-host/gpex.h"
#include "hw/usb/usb.h"
#include "net/net.h"
#include "system/kvm.h"
#include "system/qtest.h"
#include "system/reset.h"
#include "system/runstate.h"
@@ -157,21 +156,6 @@ static const MemoryRegionOps loongson3_pm_ops = {
static uint64_t get_cpu_freq_hz(const MIPSCPU *cpu)
{
#ifdef CONFIG_KVM
int ret;
uint64_t freq;
struct kvm_one_reg freq_reg = {
.id = KVM_REG_MIPS_COUNT_HZ,
.addr = (uintptr_t)(&freq)
};
if (kvm_enabled()) {
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_ONE_REG, &freq_reg);
if (ret >= 0) {
return freq * 2;
}
}
#endif
return DEF_LOONGSON3_FREQ;
}
@@ -511,8 +495,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
MemoryRegion *iomem = g_new(MemoryRegion, 1);
MemoryRegion *iocsr = g_new(MemoryRegion, 1);
/* TODO: TCG will support all CPU types */
if (!kvm_enabled()) {
/* TODO: Support all CPU types */
if (!machine->cpu_type) {
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
}
@@ -520,15 +503,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
error_report("Loongson-3/TCG needs a Loongson-3 series cpu");
exit(1);
}
} else {
if (!machine->cpu_type) {
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
}
if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
exit(1);
}
}
if (ram_size < 512 * MiB) {
error_report("Loongson-3 machine needs at least 512MB memory");
@@ -545,8 +519,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX);
/* IPI controller is in kernel for KVM */
if (!kvm_enabled()) {
ipi = qdev_new(TYPE_LOONGSON_IPI);
qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
@@ -554,7 +526,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
memory_region_add_subregion(iocsr, MAIL_SEND_ADDR,
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
}
liointc = qdev_new("loongson.liointc");
sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
@@ -575,6 +546,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
int node = i / LOONGSON3_CORE_PER_NODE;
int core = i % LOONGSON3_CORE_PER_NODE;
int ip;
hwaddr ipi_base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
@@ -584,12 +556,8 @@ static void mips_loongson3_virt_init(MachineState *machine)
cpu_mips_clock_init(cpu);
qemu_register_reset(i ? generic_cpu_reset : main_cpu_reset, cpu);
if (!kvm_enabled()) {
hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
base += core * 0x100;
qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
}
sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, ipi_base + core * 0x100);
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
MemoryRegion *core_iocsr = g_new(MemoryRegion, 1);

1
hw/mips/malta.c
View File

@@ -55,7 +55,6 @@
#include "system/system.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "system/kvm.h"
#include "semihosting/semihost.h"
#include "hw/mips/cps.h"
#include "hw/core/qdev-clock.h"

6
hw/mips/mips_int.c
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@@ -23,8 +23,6 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "hw/core/irq.h"
#include "system/kvm.h"
#include "kvm_mips.h"
#include "target/mips/cpu.h"
static void cpu_mips_irq_request(void *opaque, int irq, int level)
@@ -45,10 +43,6 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
}
if (kvm_enabled() && (irq == 2 || irq == 3)) {
kvm_mips_set_interrupt(cpu, irq, level);
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {

2
meson.build
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@@ -282,8 +282,6 @@ elif cpu == 's390x'
kvm_targets = ['s390x-softmmu']
elif cpu == 'ppc64'
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
elif cpu == 'mips64'
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
elif cpu == 'riscv64'
kvm_targets = ['riscv64-softmmu']
elif cpu == 'loongarch64'

5
target/mips/cpu.c
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@@ -25,9 +25,7 @@
#include "qapi/error.h"
#include "cpu.h"
#include "internal.h"
#include "kvm_mips.h"
#include "qemu/module.h"
#include "system/kvm.h"
#include "system/qtest.h"
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev-clock.h"
@@ -416,9 +414,6 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
/* UHI interface can be used to obtain argc and argv */
env->active_tc.gpr[4] = -1;
}
if (kvm_enabled()) {
kvm_mips_reset_vcpu(cpu);
}
#endif
}

1283
target/mips/kvm.c
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File diff suppressed because it is too large Load Diff

28
target/mips/kvm_mips.h
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@@ -1,28 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* KVM/MIPS: MIPS specific KVM APIs
*
* Copyright (C) 2012-2014 Imagination Technologies Ltd.
* Authors: Sanjay Lal <sanjayl@kymasys.com>
*/
#ifndef KVM_MIPS_H
#define KVM_MIPS_H
#include "cpu.h"
/**
* kvm_mips_reset_vcpu:
* @cpu: MIPSCPU
*
* Called at reset time to set kernel registers to their initial values.
*/
void kvm_mips_reset_vcpu(MIPSCPU *cpu);
int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level);
int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level);
#endif /* KVM_MIPS_H */

6
target/mips/meson.build
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@@ -13,11 +13,7 @@ if have_system
subdir('system')
endif
if 'CONFIG_TCG' in config_all_accel
subdir('tcg')
endif
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
subdir('tcg')
target_arch += {'mips': mips_ss}
target_system_arch += {'mips': mips_system_ss}

10
target/mips/system/cp0_timer.c
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@@ -23,7 +23,6 @@
#include "qemu/osdep.h"
#include "hw/core/irq.h"
#include "qemu/timer.h"
#include "system/kvm.h"
#include "internal.h"
/* MIPS R4K timer */
@@ -84,8 +83,7 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
{
/*
* This gets called from cpu_state_reset(), potentially before timer init.
* So env->timer may be NULL, which is also the case with KVM enabled so
* treat timer as disabled in that case.
* So env->timer may be NULL, so treat timer as disabled in that case.
*/
MIPSCPU *cpu = env_archcpu(env);
if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
@@ -141,11 +139,5 @@ void cpu_mips_clock_init(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
/*
* If we're in KVM mode, don't create the periodic timer, that is handled in
* kernel.
*/
if (!kvm_enabled()) {
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
}
}

1
target/mips/system/physaddr.c
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@@ -126,7 +126,6 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
#endif
int ret = TLBRET_MATCH;
/* effective address (modified for KVM T&E kernel segments) */
target_ulong address = real_address;
if (address <= USEG_LIMIT) {