From 750d25fc6615ff4db87bcf3a6b46e7266e59f5ae Mon Sep 17 00:00:00 2001 From: Anton Johansson Date: Wed, 30 Apr 2025 14:17:46 +0200 Subject: [PATCH] configs/target: Implement per-binary TargetInfo structure for riscv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Defines TargetInfo for 32- and 64-bit riscv binaries. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20260520-hw-riscv-cpu-int-v3-6-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé --- configs/targets/meson.build | 1 + configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 configs/targets/riscv32-softmmu.c create mode 100644 configs/targets/riscv64-softmmu.c diff --git a/configs/targets/meson.build b/configs/targets/meson.build index cca2514eb5..2ab4d27eaf 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,5 +1,6 @@ foreach target : [ 'arm-softmmu', 'aarch64-softmmu', + 'riscv32-softmmu', 'riscv64-softmmu' ] config_target_info += {target : files(target + '.c')} endforeach diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c new file mode 100644 index 0000000000..752c813077 --- /dev/null +++ b/configs/targets/riscv32-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv32) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "qemu/target-info-init.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" +#include "target/riscv/cpu-param.h" + +static const TargetInfo target_info_riscv32_system = { + .target_name = "riscv32", + .target_arch = SYS_EMU_TARGET_RISCV32, + .long_bits = 32, + .cpu_type = TYPE_RISCV_CPU, + .machine_typename = TYPE_TARGET_RISCV32_MACHINE, + .endianness = ENDIAN_MODE_LITTLE, + .page_bits_init = TARGET_PAGE_BITS, +}; + +target_info_init(target_info_riscv32_system) diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c new file mode 100644 index 0000000000..5150f0fe9d --- /dev/null +++ b/configs/targets/riscv64-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv64) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "qemu/target-info-init.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" +#include "target/riscv/cpu-param.h" + +static const TargetInfo target_info_riscv64_system = { + .target_name = "riscv64", + .target_arch = SYS_EMU_TARGET_RISCV64, + .long_bits = 64, + .cpu_type = TYPE_RISCV_CPU, + .machine_typename = TYPE_TARGET_RISCV64_MACHINE, + .endianness = ENDIAN_MODE_LITTLE, + .page_bits_init = TARGET_PAGE_BITS, +}; + +target_info_init(target_info_riscv64_system)