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target/i386: Remove AccelCPUClass::cpu_class_init need

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Expose x86_tcg_ops symbol, then directly set it as
CPUClass::tcg_ops in TYPE_X86_CPU's class_init(),
using CONFIG_TCG #ifdef'ry. No need for the
AccelCPUClass::cpu_class_init() handler anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250405161320.76854-3-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-04-05 18:13:06 +02:00
committed by Richard Henderson
parent f50d0f335a
commit a522b04bb9
3 changed files with 9 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
target/i386/cpu.c
View File

@@ -43,6 +43,7 @@
#include "hw/boards.h"
#include "hw/i386/sgx-epc.h"
#endif
#include "tcg/tcg-cpu.h"
#include "disas/capstone.h"
#include "cpu-internal.h"
@@ -8915,6 +8916,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
#ifdef CONFIG_TCG
cc->tcg_ops = &x86_tcg_ops;
#endif /* CONFIG_TCG */
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64

14
target/i386/tcg/tcg-cpu.c
View File

@@ -124,7 +124,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
const TCGCPUOps x86_tcg_ops = {
/*
* The x86 has a strong memory model with some store-after-load re-ordering
*/
@@ -152,17 +152,6 @@ static const TCGCPUOps x86_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/* for x86, all cpus use the same set of operations */
cc->tcg_ops = &x86_tcg_ops;
}
static void x86_tcg_cpu_class_init(CPUClass *cc)
{
cc->init_accel_cpu = x86_tcg_cpu_init_ops;
}
static void x86_tcg_cpu_xsave_init(void)
{
#define XO(bit, field) \
@@ -211,7 +200,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
acc->cpu_target_realize = tcg_cpu_realizefn;
#endif /* CONFIG_USER_ONLY */
acc->cpu_class_init = x86_tcg_cpu_class_init;
acc->cpu_instance_init = x86_tcg_cpu_instance_init;
}
static const TypeInfo x86_tcg_cpu_accel_type_info = {

4
target/i386/tcg/tcg-cpu.h
View File

@@ -19,6 +19,8 @@
#ifndef TCG_CPU_H
#define TCG_CPU_H
#include "cpu.h"
#define XSAVE_FCW_FSW_OFFSET 0x000
#define XSAVE_FTW_FOP_OFFSET 0x004
#define XSAVE_CWD_RIP_OFFSET 0x008
@@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFF
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET);
extern const TCGCPUOps x86_tcg_ops;
bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
int x86_mmu_index_pl(CPUX86State *env, unsigned pl);