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target/rx: Factor mo_endian() helper out

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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-10-09 16:55:33 +02:00
parent 363fff6d1b
commit cb8e4556d5
1 changed files with 9 additions and 4 deletions
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13
target/rx/translate.c
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@@ -72,6 +72,11 @@ static TCGv_i64 cpu_acc;
#define cpu_sp cpu_regs[0]
static inline MemOp mo_endian(DisasContext *dc)
{
return MO_TE;
}
/* decoder helper */
static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
int i, int n)
@@ -163,19 +168,19 @@ static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx, vaddr dest)
/* generic load wrapper */
static inline void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv reg, TCGv mem)
{
tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | mo_endian(ctx));
}
/* unsigned load wrapper */
static inline void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv reg, TCGv mem)
{
tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE);
tcg_gen_qemu_ld_i32(reg, mem, 0, size | mo_endian(ctx));
}
/* generic store wrapper */
static inline void rx_gen_st(DisasContext *ctx, MemOp size, TCGv reg, TCGv mem)
{
tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
tcg_gen_qemu_st_i32(reg, mem, 0, size | mo_endian(ctx));
}
/* [ri, rb] */
@@ -226,7 +231,7 @@ static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem,
if (ld < 3) {
mop = mi_to_mop(mi);
addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs);
tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE);
tcg_gen_qemu_ld_i32(mem, addr, 0, mop | mo_endian(ctx));
return mem;
} else {
return cpu_regs[rs];