mirror of
https://github.com/qemu/qemu.git
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* more WHPX fixes and documentation * hpet: fix bounds check for s->timer[] * hpet: lower HPET_MAX_TIMERS to 24 * lsi53c895a: keep SCSIRequest alive during DMA * lsi53c895a: keep device alive during SCRIPTS execution * hw/acpi: fix save/restore for MIPS Malta machine # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmnKTQ0UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNDAQgAry87O2EtgZBK8084Rn41+8w7Hx4K # HmKGGLRHunZgOPPbFtLFj8sjmZGqV6MuELf8zBIwheJiaWyp9SqPN2FtwldEwLsG # C37MsUS02SbfPrJPuAMaDsfeFknHaV/pUWiZIYr5S5+dKckz8P9RUZghCVKBmwyL # mapNE7/++A2HCX2FnABmAsMMo+kt425kCmkDFryJQ9R7j8vjYo2sHn+WpDRjOLYS # 0K7a5HBCwE+TrdZC1Q3J17VMhX/sFL/Ms8ByIhwJa+WimZoF/roaDBiK/0iUfVlg # 196U0rvejdymAMWqIU462fyHvVkeW50FCHjTccmqnrIbFEdL4CFZlnrNxQ== # =JIqb # -----END PGP SIGNATURE----- # gpg: Signature made Mon Mar 30 11:14:37 2026 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: hw/acpi: Do not save/load cpuhp state unconditionally lsi53c895a: keep SCSIRequest alive during DMA lsi53c895a: keep lsi_request alive as long as the SCSIRequest lsi53c895a: keep lsi_request and SCSIRequest in local variables lsi53c895a: do not do anything else if a reset is requested by writing ISTAT0 lsi53c895a: keep a reference to the device while SCRIPTS execute hpet: lower HPET_MAX_TIMERS to 24 hpet: fix bounds check for s->timer[] target/i386: emulate: remove redundant logging for unmapped MMIO access whpx: i386: trace unsupported MSR accesses docs: add WHPX section with initial info meson.build: remove i386-softmmu WHPX support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
@@ -184,10 +184,18 @@ static const VMStateDescription vmstate_tco_io_state = {
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}
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};
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static bool cpuhp_needed(void *opaque)
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{
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MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
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return mc->has_hotpluggable_cpus;
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}
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static const VMStateDescription vmstate_cpuhp_state = {
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.name = "ich9_pm/cpuhp",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpuhp_needed,
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.fields = (const VMStateField[]) {
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VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs),
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VMSTATE_END_OF_LIST()
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@@ -195,10 +195,18 @@ static const VMStateDescription vmstate_memhp_state = {
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}
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};
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static bool cpuhp_needed(void *opaque)
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{
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MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
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return mc->has_hotpluggable_cpus;
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}
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static const VMStateDescription vmstate_cpuhp_state = {
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.name = "piix4_pm/cpuhp",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpuhp_needed,
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.fields = (const VMStateField[]) {
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VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
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VMSTATE_END_OF_LIST()
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@@ -197,6 +197,7 @@ typedef struct lsi_request {
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uint8_t *dma_buf;
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uint32_t pending;
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int out;
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bool orphan;
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QTAILQ_ENTRY(lsi_request) next;
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} lsi_request;
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@@ -626,6 +627,8 @@ static void lsi_do_dma(LSIState *s, int out)
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uint32_t count;
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dma_addr_t addr;
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SCSIDevice *dev;
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SCSIRequest *req;
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lsi_request *p;
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if (!s->current || !s->current->dma_len) {
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/* Wait until data is available. */
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@@ -633,12 +636,14 @@ static void lsi_do_dma(LSIState *s, int out)
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return;
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}
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dev = s->current->req->dev;
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p = s->current;
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req = scsi_req_ref(s->current->req);
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dev = req->dev;
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assert(dev);
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count = s->dbc;
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if (count > s->current->dma_len)
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count = s->current->dma_len;
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if (count > p->dma_len)
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count = p->dma_len;
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addr = s->dnad;
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/* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
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@@ -653,21 +658,27 @@ static void lsi_do_dma(LSIState *s, int out)
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s->csbc += count;
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s->dnad += count;
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s->dbc -= count;
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if (s->current->dma_buf == NULL) {
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s->current->dma_buf = scsi_req_get_buf(s->current->req);
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if (p->dma_buf == NULL) {
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p->dma_buf = scsi_req_get_buf(req);
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}
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/* ??? Set SFBR to first data byte. */
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if (out) {
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lsi_mem_read(s, addr, s->current->dma_buf, count);
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lsi_mem_read(s, addr, p->dma_buf, count);
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} else {
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lsi_mem_write(s, addr, s->current->dma_buf, count);
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lsi_mem_write(s, addr, p->dma_buf, count);
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}
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s->current->dma_len -= count;
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if (s->current->dma_len == 0) {
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s->current->dma_buf = NULL;
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scsi_req_continue(s->current->req);
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if (p->orphan) {
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scsi_req_unref(req);
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return;
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}
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scsi_req_unref(req);
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p->dma_len -= count;
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if (p->dma_len == 0) {
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p->dma_buf = NULL;
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scsi_req_continue(req);
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} else {
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s->current->dma_buf += count;
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p->dma_buf += count;
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lsi_resume_script(s);
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}
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}
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@@ -743,14 +754,20 @@ static lsi_request *lsi_find_by_tag(LSIState *s, uint32_t tag)
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return NULL;
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}
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static void lsi_request_free(LSIState *s, lsi_request *p)
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static void lsi_request_orphan(LSIState *s, lsi_request *p)
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{
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p->orphan = true;
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if (p == s->current) {
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s->current = NULL;
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} else {
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QTAILQ_REMOVE(&s->queue, p, next);
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}
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g_free(p);
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scsi_req_unref(p->req);
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}
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static void lsi_free_request(SCSIBus *bus, void *priv)
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{
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g_free(priv);
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}
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static void lsi_request_cancelled(SCSIRequest *req)
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@@ -758,9 +775,7 @@ static void lsi_request_cancelled(SCSIRequest *req)
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LSIState *s = LSI53C895A(req->bus->qbus.parent);
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lsi_request *p = req->hba_private;
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req->hba_private = NULL;
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lsi_request_free(s, p);
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scsi_req_unref(req);
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lsi_request_orphan(s, p);
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}
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/* Record that data is available for a queued command. Returns zero if
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@@ -812,9 +827,7 @@ static void lsi_command_complete(SCSIRequest *req, size_t resid)
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}
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if (req->hba_private == s->current) {
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req->hba_private = NULL;
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lsi_request_free(s, s->current);
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scsi_req_unref(req);
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lsi_request_orphan(s, s->current);
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}
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if (!stop) {
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lsi_resume_script(s);
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@@ -825,10 +838,11 @@ static void lsi_command_complete(SCSIRequest *req, size_t resid)
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static void lsi_transfer_data(SCSIRequest *req, uint32_t len)
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{
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LSIState *s = LSI53C895A(req->bus->qbus.parent);
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lsi_request *p = req->hba_private;
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int out;
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assert(req->hba_private);
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if (s->waiting == LSI_WAIT_RESELECT || req->hba_private != s->current ||
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assert(!p->orphan);
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if (s->waiting == LSI_WAIT_RESELECT || p != s->current ||
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(lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON))) {
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if (lsi_queue_req(s, req, len)) {
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return;
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@@ -1163,6 +1177,7 @@ static void lsi_execute_script(LSIState *s)
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s->waiting = LSI_NOWAIT;
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}
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object_ref(s);
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reentrancy_level++;
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s->istat1 |= LSI_ISTAT1_SRUN;
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@@ -1182,6 +1197,7 @@ again:
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s->waiting = LSI_WAIT_SCRIPTS;
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lsi_scripts_timer_start(s);
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reentrancy_level--;
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object_unref(s);
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return;
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}
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insn = read_dword(s, s->dsp);
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@@ -1630,6 +1646,7 @@ again:
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trace_lsi_execute_script_stop();
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reentrancy_level--;
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object_unref(s);
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}
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static uint8_t lsi_reg_readb(LSIState *s, int offset)
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@@ -1946,6 +1963,10 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
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CASE_SET_REG32(dsa, 0x10)
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case 0x14: /* ISTAT0 */
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s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
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if (val & LSI_ISTAT0_SRST) {
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device_cold_reset(DEVICE(s));
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return;
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}
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if (val & LSI_ISTAT0_ABRT) {
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lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
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}
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@@ -1959,9 +1980,6 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
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s->dsp = s->dnad;
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lsi_execute_script(s);
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}
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if (val & LSI_ISTAT0_SRST) {
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device_cold_reset(DEVICE(s));
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}
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break;
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case 0x16: /* MBOX0 */
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s->mbox0 = val;
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@@ -2316,7 +2334,8 @@ static const struct SCSIBusInfo lsi_scsi_info = {
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.transfer_data = lsi_transfer_data,
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.complete = lsi_command_complete,
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.cancel = lsi_request_cancelled
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.cancel = lsi_request_cancelled,
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.free_request = lsi_free_request,
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};
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static void scripts_timer_cb(void *opaque)
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@@ -464,13 +464,14 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
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}
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} else {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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HPETTimer *timer = &s->timer[timer_id];
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HPETTimer *timer;
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if (timer_id > s->num_timers) {
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if (timer_id >= s->num_timers) {
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trace_hpet_timer_id_out_of_range(timer_id);
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return 0;
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}
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timer = &s->timer[timer_id];
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switch (addr & 0x1f) {
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case HPET_TN_CFG: // including interrupt capabilities
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return timer->config >> shift;
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@@ -564,13 +565,15 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
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}
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} else {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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HPETTimer *timer = &s->timer[timer_id];
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HPETTimer *timer;
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trace_hpet_ram_write_timer_id(timer_id);
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if (timer_id > s->num_timers) {
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if (timer_id >= s->num_timers) {
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trace_hpet_timer_id_out_of_range(timer_id);
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return;
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}
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timer = &s->timer[timer_id];
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switch (addr & 0x18) {
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case HPET_TN_CFG:
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trace_hpet_ram_write_tn_cfg(addr & 4);
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