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disas/riscv: enable mnret disassembly

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The translator has supported mnret since commit 3157a553ec
("target/riscv: Add Smrnmi mnret instruction"), but the
disassembler still renders it as illegal. Add it unguarded,
since the encoding does not overlap any other extension.

Signed-off-by: imaginos <imaginos32@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260614141315.17320-1-imaginos32@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
imaginos
2026-06-14 16:12:24 +02:00
committed by Alistair Francis
parent 66e4d3517b
commit dd595103db
1 changed files with 7 additions and 0 deletions
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7
disas/riscv.c
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@@ -989,6 +989,7 @@ typedef enum {
rv_op_cbo_clean = 957,
rv_op_cbo_flush = 958,
rv_op_cbo_zero = 959,
rv_op_mnret = 960,
} rv_op;
/* register names */
@@ -2263,6 +2264,7 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -4077,6 +4079,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 64: op = rv_op_mret; break;
}
break;
case 1792:
switch ((inst >> 15) & 0b1111111111) {
case 64: op = rv_op_mnret; break;
}
break;
case 1952:
switch ((inst >> 15) & 0b1111111111) {
case 576: op = rv_op_dret; break;