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target/riscv: Remove AccelCPUClass::cpu_class_init need

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Expose riscv_tcg_ops symbol, then directly set it as
CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(),
using CONFIG_TCG #ifdef'ry. No need for the
AccelCPUClass::cpu_class_init() handler anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250405161320.76854-2-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-04-05 18:13:05 +02:00
committed by Richard Henderson
parent 84cde4af08
commit f50d0f335a
3 changed files with 6 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
target/riscv/cpu.c
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@@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
cc->get_arch_id = riscv_get_arch_id;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_ops = &riscv_tcg_ops;
#endif /* CONFIG_TCG */
device_class_set_props(dc, riscv_cpu_properties);
}

16
target/riscv/tcg/tcg-cpu.c
View File

@@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
env->excp_uw2 = data[2];
}
static const TCGCPUOps riscv_tcg_ops = {
const TCGCPUOps riscv_tcg_ops = {
.guest_default_memory_order = 0,
.initialize = riscv_translate_init,
@@ -1527,24 +1527,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
}
}
static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
* All cpus use the same set of operations.
*/
cc->tcg_ops = &riscv_tcg_ops;
}
static void riscv_tcg_cpu_class_init(CPUClass *cc)
{
cc->init_accel_cpu = riscv_tcg_cpu_init_ops;
}
static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
{
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
acc->cpu_class_init = riscv_tcg_cpu_class_init;
acc->cpu_instance_init = riscv_tcg_cpu_instance_init;
acc->cpu_target_realize = riscv_tcg_cpu_realize;
}

2
target/riscv/tcg/tcg-cpu.h
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@@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
extern const TCGCPUOps riscv_tcg_ops;
struct DisasContext;
struct RISCVCPUConfig;
typedef struct RISCVDecoder {