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target/hexagon: Explode MO_TExx -> MO_TE | MO_xx

Browse Source 
Extract the implicit MO_TE definition in order to replace
it in the next commit.

Mechanical change using:

  $ for n in UW UL UQ UO SW SL SQ; do \
      sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
           $(git grep -l MO_TE$n target/hexagon); \
    done

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20250312103238.99981-2-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-03-12 10:16:53 +01:00
parent 019fbfa4bc
commit fdcb7483ae
3 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
target/hexagon/genptr.c
View File

@@ -329,14 +329,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
{
tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TE | MO_UL);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
{
tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TE | MO_UQ);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
@@ -756,7 +756,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
{
Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
CHECK_NOSHUF(EA, 8);
tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ);
tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TE | MO_UQ);
}
#ifndef CONFIG_HEXAGON_IDEF_PARSER
@@ -1230,7 +1230,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
}
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TE | MO_UQ);
tcg_gen_addi_tl(src, src, 8);
tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8);
}

10
target/hexagon/macros.h
View File

@@ -115,27 +115,27 @@
#define MEM_LOAD2s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TE | MO_SW); \
} while (0)
#define MEM_LOAD2u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TE | MO_UW); \
} while (0)
#define MEM_LOAD4s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TE | MO_SL); \
} while (0)
#define MEM_LOAD4u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TE | MO_UL); \
} while (0)
#define MEM_LOAD8u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 8); \
tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TE | MO_UQ); \
} while (0)
#define MEM_STORE1_FUNC(X) \

6
target/hexagon/translate.c
View File

@@ -656,17 +656,17 @@ void process_store(DisasContext *ctx, int slot_num)
case 2:
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUW);
ctx->mem_idx, MO_TE | MO_UW);
break;
case 4:
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUL);
ctx->mem_idx, MO_TE | MO_UL);
break;
case 8:
tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUQ);
ctx->mem_idx, MO_TE | MO_UQ);
break;
default:
{