[PR #305] [CLOSED] Adding initial support for Neorv32 RiscV MCU #417

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opened 2026-01-31 21:31:11 +00:00 by claunia · 0 comments
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📋 Pull Request Information

Original PR: https://github.com/qemu/qemu/pull/305
Author: @VideoGPU
Created: 10/19/2025
Status: Closed

Base: masterHead: mlevit_neorv32_riscv_support


📝 Commits (1)

  • 35fd716 Adding initial support for Neorv32 RiscV MCU

📊 Changes

28 files changed (+1843 additions, -0 deletions)

View changed files

📝 .gitignore (+1 -0)
📝 configs/devices/riscv32-softmmu/default.mak (+1 -0)
docs/system/riscv/neorv32.rst (+110 -0)
📝 hw/char/Kconfig (+3 -0)
📝 hw/char/meson.build (+1 -0)
hw/char/neorv32_uart.c (+311 -0)
📝 hw/misc/Kconfig (+2 -0)
📝 hw/misc/meson.build (+1 -0)
hw/misc/neorv32_sysinfo.c (+183 -0)
hw/misc/neorv32_sysinfo.h (+79 -0)
hw/misc/neorv32_sysinfo_rtl.h (+134 -0)
📝 hw/riscv/Kconfig (+8 -0)
📝 hw/riscv/meson.build (+1 -0)
hw/riscv/neorv32.c (+219 -0)
📝 hw/ssi/Kconfig (+4 -0)
📝 hw/ssi/meson.build (+1 -0)
hw/ssi/neorv32_spi.c (+504 -0)
include/hw/char/neorv32_uart.h (+68 -0)
include/hw/riscv/neorv32.h (+60 -0)
include/hw/ssi/neorv32_spi.h (+70 -0)

...and 8 more files

📄 Description

  1. IMEM, DMEM memory regions, bootloader ROM

  2. Basic support for UART0 (no interrupts yet)

  3. Based on Neorv32 RTL implementation repo
    https://github.com/stnolting/neorv32
    commit id 7d0ef6b2

  4. QEMU build configuration:


/path/to/qemu/configure
--python=/usr/local/bin/python3.12
--target-list=riscv32-softmmu
--enable-fdt
--enable-debug
--disable-vnc
--disable-gtk


🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.

## 📋 Pull Request Information **Original PR:** https://github.com/qemu/qemu/pull/305 **Author:** [@VideoGPU](https://github.com/VideoGPU) **Created:** 10/19/2025 **Status:** ❌ Closed **Base:** `master` ← **Head:** `mlevit_neorv32_riscv_support` --- ### 📝 Commits (1) - [`35fd716`](https://github.com/qemu/qemu/commit/35fd716fa4ed07a03afac2ea6e7ab1e754d5deb3) Adding initial support for Neorv32 RiscV MCU ### 📊 Changes **28 files changed** (+1843 additions, -0 deletions) <details> <summary>View changed files</summary> 📝 `.gitignore` (+1 -0) 📝 `configs/devices/riscv32-softmmu/default.mak` (+1 -0) ➕ `docs/system/riscv/neorv32.rst` (+110 -0) 📝 `hw/char/Kconfig` (+3 -0) 📝 `hw/char/meson.build` (+1 -0) ➕ `hw/char/neorv32_uart.c` (+311 -0) 📝 `hw/misc/Kconfig` (+2 -0) 📝 `hw/misc/meson.build` (+1 -0) ➕ `hw/misc/neorv32_sysinfo.c` (+183 -0) ➕ `hw/misc/neorv32_sysinfo.h` (+79 -0) ➕ `hw/misc/neorv32_sysinfo_rtl.h` (+134 -0) 📝 `hw/riscv/Kconfig` (+8 -0) 📝 `hw/riscv/meson.build` (+1 -0) ➕ `hw/riscv/neorv32.c` (+219 -0) 📝 `hw/ssi/Kconfig` (+4 -0) 📝 `hw/ssi/meson.build` (+1 -0) ➕ `hw/ssi/neorv32_spi.c` (+504 -0) ➕ `include/hw/char/neorv32_uart.h` (+68 -0) ➕ `include/hw/riscv/neorv32.h` (+60 -0) ➕ `include/hw/ssi/neorv32_spi.h` (+70 -0) _...and 8 more files_ </details> ### 📄 Description 1) IMEM, DMEM memory regions, bootloader ROM 2) Basic support for UART0 (no interrupts yet) 3) Based on Neorv32 RTL implementation repo https://github.com/stnolting/neorv32 commit id 7d0ef6b2 4) QEMU build configuration: ------------------------ /path/to/qemu/configure \ --python=/usr/local/bin/python3.12 \ --target-list=riscv32-softmmu \ --enable-fdt \ --enable-debug \ --disable-vnc \ --disable-gtk --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>
claunia added the pull-request label 2026-01-31 21:31:11 +00:00
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Reference: starred/qemu#417