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[PR #305] Adding initial support for Neorv32 RiscV MCU #422

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opened 2026-01-31 21:31:12 +00:00 by claunia · 0 comments
claunia commented 2026-01-31 21:31:12 +00:00
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Original Pull Request: https://github.com/qemu/qemu/pull/305

State: closed
Merged: No

  1. IMEM, DMEM memory regions, bootloader ROM

  2. Basic support for UART0 (no interrupts yet)

  3. Based on Neorv32 RTL implementation repo
    https://github.com/stnolting/neorv32
    commit id 7d0ef6b2

  4. QEMU build configuration:

/path/to/qemu/configure
--python=/usr/local/bin/python3.12
--target-list=riscv32-softmmu
--enable-fdt
--enable-debug
--disable-vnc
--disable-gtk

**Original Pull Request:** https://github.com/qemu/qemu/pull/305 **State:** closed **Merged:** No --- 1) IMEM, DMEM memory regions, bootloader ROM 2) Basic support for UART0 (no interrupts yet) 3) Based on Neorv32 RTL implementation repo https://github.com/stnolting/neorv32 commit id 7d0ef6b2 4) QEMU build configuration: ------------------------ /path/to/qemu/configure \ --python=/usr/local/bin/python3.12 \ --target-list=riscv32-softmmu \ --enable-fdt \ --enable-debug \ --disable-vnc \ --disable-gtk
claunia added the pull-request label 2026-01-31 21:31:12 +00:00
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Reference: starred/qemu#422
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