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Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
104 lines
4.8 KiB
ReStructuredText
104 lines
4.8 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-or-later
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.. _Hexagon-System-emulator:
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Hexagon System emulator
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-----------------------
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Use the ``qemu-system-hexagon`` executable to simulate a 32-bit Hexagon
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machine.
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Hexagon Machines
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================
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Hexagon DSPs are suited to various functions and generally appear in a
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"DSP subsystem" of a larger system-on-chip (SoC).
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Hexagon DSPs are often included in a subsystem that looks like the diagram
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below. Instructions are loaded into DDR before the DSP is brought out of
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reset and the first instructions are fetched from DDR via the EVB/reset vector.
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In a real system, a TBU/SMMU would normally arbitrate AXI accesses but
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we don't have a need to model that for QEMU.
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Hexagon DSP cores use simultaneous multithreading (SMT) with as many as 8
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hardware threads.
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.. admonition:: Diagram
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.. code:: text
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AHB (local) bus AXI (global) bus
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│ │
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│ │
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┌─────────┐ │ ┌─────────────────┐ │
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│ L2VIC ├──┤ │ │ │
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│ ├──┼───────► ├───────┤
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└─────▲───┘ │ │ Hexagon DSP │ │
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│ │ │ │ │ ┌─────┐
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│ │ │ N threads │ │ │ DDR │
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│ ├───────┤ │ │ │ │
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┌────┴──┐ │ │ │ ├────────┤ │
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│QTimer ├───┤ │ │ │ │ │
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│ │ │ │ │ │ │ │
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└───────┘ │ │ ┌─────────┐ │ │ │ │
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│ │ ┌─────────┐│ │ │ │ │
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┌───────┐ │ │ │ HVX xM ││ │ │ │ │
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│QDSP6SS├───┤ │ │ │┘ │ │ │ │
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└───────┘ │ │ └─────────┘ │ │ └─────┘
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│ │ │ │
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┌───────┐ │ └─────────────────┘ │
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│ CSR ├───┤
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└───────┘ │ ┌──────┐ ┌───────────┐
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│ │ TCM │ │ VTCM │
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│ │ │ │
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└──────┘ │ │
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│ │
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│ │
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│ │
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└───────────┘
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Components
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----------
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Other than l2vic and HVX, the components below are not implemented in QEMU.
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* L2VIC: the L2 vectored interrupt controller. Supports 1024 input
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interrupts, edge- or level-triggered. The core ISA has system registers
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``VID``, ``VID1`` which read through to the L2VIC device.
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* QTimer: ARMSSE-based programmable timer device. Its interrupts are
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wired to the L2VIC. System registers ``TIMER``, ``UTIMER`` read
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through to the QTimer device.
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* QDSP6SS: DSP subsystem features, accessible to the entire SoC, including
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DSP NMI, watchdog, reset, etc.
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* CSR: Configuration/Status Registers.
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* TCM: DSP-exclusive tightly-coupled memory. This memory can be used for
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DSPs when isolated from DDR and in some bootstrapping modes.
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* VTCM: DSP-exclusive vector tightly-coupled memory. This memory is accessed
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by some HVX instructions.
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* HVX: the vector coprocessor supports 64 and 128-byte vector registers.
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64-byte mode is not implemented in QEMU.
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Bootstrapping
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-------------
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Hexagon systems do not generally have access to a block device. So, for
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QEMU the typical use case involves loading a binary or ELF file into memory
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and executing from the indicated start address::
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$ qemu-system-hexagon -kernel ./prog -append 'arg1 arg2'
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Semihosting
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-----------
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Hexagon supports a semihosting interface similar to other architectures'.
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The ``trap0`` instruction can activate these semihosting calls so that the
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guest software can access the host console and filesystem. Semihosting
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is not yet implemented in QEMU hexagon.
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Hexagon Features
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================
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.. toctree::
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hexagon/emulation
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hexagon/cdsp
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