Files
qemu/hw/arm/smmuv3-accel-stubs.c
Shameer Kolothum 6a51b66dd5 hw/arm/smmuv3-accel: Fix veventq read returning true on EAGAIN/EINTR
smmuv3_accel_event_read_validate() returns true for EAGAIN/EINTR, but
no data has been read into the buffer. Callers treat true as success and
proceed to use the uninitialized buffer.

Change the return type to int with three distinct states:
  0  — success, buf is populated and valid
  1  — EAGAIN/EINTR, no data available
 -1  — error, @errp set

Resolves: Coverity CID 1660057
Fixes: d4aea0f75b ("hw/arm/smmuv3-accel: Introduce common helper for veventq read")
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20260625122843.107584-1-skolothumtho@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-07-06 11:32:01 +01:00

65 lines
1.3 KiB
C

/*
* Stubs for accelerated SMMU instance backed by an iommufd vIOMMU object.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/smmuv3.h"
#include "hw/arm/smmuv3-accel.h"
bool smmuv3_accel_init(SMMUv3State *s, Error **errp)
{
error_setg(errp, "accel=on support not compiled in");
return false;
}
bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,
Error **errp)
{
return true;
}
bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range,
Error **errp)
{
return true;
}
bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp)
{
return true;
}
bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,
Error **errp)
{
return true;
}
void smmuv3_accel_idr_override(SMMUv3State *s)
{
}
bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)
{
return true;
}
int smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t type,
void *buf, size_t size, Error **errp)
{
return 0;
}
void smmuv3_accel_reset(SMMUv3State *s)
{
}
SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj)
{
return SMMUV3_CMDQV_NONE;
}