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20df4ef1c9
A conflict exists when any GPR is written by multiple instructions and at least one write is unconditional. This catches (1) two unconditional writes to the same GPR and (2) an unconditional write combined with a predicated write. Add HEX_CAUSE_REG_WRITE_CONFLICT and map it to SIGILL. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2696 Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/*
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* Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_INSN_H
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#define HEXAGON_INSN_H
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#include "cpu.h"
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#define INSTRUCTIONS_MAX 7 /* 2 pairs + loopend */
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#define REG_OPERANDS_MAX 5
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#define IMMEDS_MAX 2
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struct Instruction;
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struct Packet;
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struct DisasContext;
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typedef void (*SemanticInsn)(struct DisasContext *ctx);
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struct Instruction {
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SemanticInsn generate; /* pointer to genptr routine */
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uint8_t regno[REG_OPERANDS_MAX]; /* reg operands including predicates */
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uint16_t opcode;
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uint32_t iclass:6;
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uint32_t slot:3;
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uint32_t which_extended:1; /* If has an extender, which immediate */
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uint32_t new_value_producer_slot:4;
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int32_t new_read_idx;
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int32_t dest_idx;
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bool dest_is_pair;
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bool dest_is_gpr;
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bool has_pred_dest;
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bool part1; /*
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* cmp-jumps are split into two insns.
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* set for the compare and clear for the jump
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*/
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bool extension_valid; /* Has a constant extender attached */
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bool is_endloop; /* This is an end of loop */
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int32_t immed[IMMEDS_MAX]; /* immediate field */
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};
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typedef struct Instruction Insn;
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struct Packet {
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uint16_t num_insns;
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uint16_t encod_pkt_size_in_bytes;
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uint32_t pc;
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/* Pre-decodes about COF */
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bool pkt_has_cof; /* Has any change-of-flow */
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bool pkt_has_multi_cof; /* Has more than one change-of-flow */
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bool pkt_has_endloop;
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bool pkt_has_dczeroa;
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bool pkt_has_scalar_store_s0;
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bool pkt_has_scalar_store_s1;
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bool pkt_has_hvx;
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Insn *vhist_insn;
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bool pkt_has_write_conflict;
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Insn insn[INSTRUCTIONS_MAX];
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};
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typedef struct Packet Packet;
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#endif
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