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qemu/target/riscv/insn_trans
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Philippe Mathieu-Daudé 11c2c6e025 target/riscv: Initialize DisasContext::mo_endian once 
The data access endianness is constant during a translation
block; rather than calling the mo_endian() method each time,
initialize the DisasContext::mo_endianness field once in
TranslatorOps::init_disas_context().

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20260527201348.29511-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-06-16 13:38:50 +10:00
..
trans_privileged.c.inc
target/riscv: Fix size of badaddr and bins
2026-06-15 13:10:14 +10:00
trans_rva.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvb.c.inc
target/riscv: Drop tcg_temp_free
2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc
target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions
2025-05-19 13:39:10 +10:00
trans_rvd.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvf.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvh.c.inc
target/riscv: update decode_save_opc to store extra word2
2024-10-30 11:22:08 +10:00
trans_rvi.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvk.c.inc
target/riscv: Drop tcg_temp_free
2023-03-05 13:44:08 -08:00
trans_rvm.c.inc
target/riscv: Fix size of retxh
2026-06-15 13:10:14 +10:00
trans_rvv.c.inc
target/riscv: Fix size of vector CSRs
2026-06-15 13:10:14 +10:00
trans_rvvk.c.inc
target/riscv: rvv: Allow fractional LMUL on vector SHA instructions
2026-04-29 13:38:13 +10:00
trans_rvzabha.c.inc
target/riscv: Conceal MO_TE within gen_cmpxchg*()
2025-10-24 09:24:08 +10:00
trans_rvzacas.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvzalasr.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvzawrs.c.inc
target/riscv: Raise exceptions on wrs.nto
2024-06-03 11:12:11 +10:00
trans_rvzce.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvzcmop.c.inc
target/riscv: Add zcmop extension
2024-07-18 12:00:42 +10:00
trans_rvzfa.c.inc
tcg: Rename cpu_env to tcg_env
2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvzicbo.c.inc
target/riscv/insn_trans/trans_rvzicbo.c.inc: save opcode before helpers
2026-06-15 13:10:14 +10:00
trans_rvzicfiss.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_rvzicond.c.inc
target/riscv: refactor Zicond support
2023-05-05 10:49:50 +10:00
trans_rvzimop.c.inc
target/riscv: Add zimop extension
2024-07-18 12:00:42 +10:00
trans_svinval.c.inc
target/riscv: Reject Svinval instructions in U-mode
2026-06-15 13:10:14 +10:00
trans_xlrbr.c.inc
target/riscv: add draft RISC-V Zbr ext as xbr0p93
2026-04-29 11:41:00 +10:00
trans_xmips.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_xthead.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00
trans_xventanacondops.c.inc
target/riscv: redirect XVentanaCondOps to use the Zicond functions
2023-05-05 10:49:50 +10:00
trans_zilsd.c.inc
target/riscv: Initialize DisasContext::mo_endian once
2026-06-16 13:38:50 +10:00