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b73a0fcf4d
pmp.h is only needed and included for system mode, however relevant macros (MAX_RISCV_PMPS, OLD_MAX_RISCV_PMPS, MIN_RISCV_PMP_GRANULARITY) are required unconditionally by cpu.c, and so are defined in cpu.h. pmp.h then defines pmp_table_t depending on these macros and so requires cpu.h, and cpu.h in turn uses pmp_table_t resulting in circular inclusion. Move PMP macros to pmp.h and only expose PMP properties in system mode. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-28-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
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* QEMU RISC-V PMP (Physical Memory Protection)
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*
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* Author: Daire McNamara, daire.mcnamara@emdalo.com
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* Ivan Griffin, ivan.griffin@emdalo.com
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*
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* This provides a RISC-V Physical Memory Protection interface
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_PMP_H
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#define RISCV_PMP_H
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#define MAX_RISCV_PMPS (64)
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#define OLD_MAX_RISCV_PMPS (16)
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#define MIN_RISCV_PMP_GRANULARITY 4
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typedef enum {
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PMP_READ = 1 << 0,
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PMP_WRITE = 1 << 1,
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PMP_EXEC = 1 << 2,
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PMP_AMATCH = (3 << 3),
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PMP_MTMATCH = (3 << 5),
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PMP_LOCK = 1 << 7
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} pmp_priv_t;
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typedef enum {
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PMP_AMATCH_OFF, /* Null (off) */
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PMP_AMATCH_TOR, /* Top of Range */
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PMP_AMATCH_NA4, /* Naturally aligned four-byte region */
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PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
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} pmp_am_t;
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typedef enum {
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MSECCFG_MML = 1 << 0,
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MSECCFG_MMWP = 1 << 1,
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MSECCFG_RLB = 1 << 2,
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MSECCFG_USEED = 1 << 8,
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MSECCFG_SSEED = 1 << 9,
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MSECCFG_MLPE = 1 << 10,
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MSECCFG_PMM = 3ULL << 32,
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} mseccfg_field_t;
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typedef struct {
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uint64_t addr_reg;
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uint8_t cfg_reg;
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} pmp_entry_t;
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typedef struct {
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hwaddr sa;
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hwaddr ea;
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} pmp_addr_t;
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typedef struct {
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pmp_entry_t pmp[MAX_RISCV_PMPS];
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pmp_addr_t addr[MAX_RISCV_PMPS];
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uint32_t num_rules;
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} pmp_table_t;
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typedef struct CPUArchState CPURISCVState;
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bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
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int size, pmp_priv_t privs,
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pmp_priv_t *allowed_privs,
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privilege_mode_t mode);
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uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
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void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
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void pmp_update_rule_nums(CPURISCVState *env);
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uint32_t pmp_get_num_rules(CPURISCVState *env);
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int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
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void pmp_unlock_entries(CPURISCVState *env);
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#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
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#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
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#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
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#endif
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