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f7f4cd501c
In preparation of removing the cpu_ldl_code() and cpu_ldq_code() wrappers, inline them. Since RISC-V instructions are always stored in little-endian order (see "Volume I: RISC-V Unprivileged ISA" document, chapter 'Instruction Encoding Spaces and Prefixes': "instruction fetch in RISC-V is little-endian"), replace MO_TE -> MO_LE. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260202214317.99090-1-philmd@linaro.org>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* RISC-V Zcmt Extension Helper for QEMU.
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*
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* Copyright (c) 2021-2022 PLCT Lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "accel/tcg/cpu-ldst.h"
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target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
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{
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unsigned mmu_index = cpu_mmu_index(env_cpu(env), true);
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MemOpIdx oi;
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#if !defined(CONFIG_USER_ONLY)
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RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
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if (ret != RISCV_EXCP_NONE) {
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riscv_raise_exception(env, ret, 0);
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}
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#endif
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target_ulong target;
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target_ulong val = env->jvt;
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int xlen = riscv_cpu_xlen(env);
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uint8_t mode = get_field(val, JVT_MODE);
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target_ulong base = val & JVT_BASE;
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target_ulong t0;
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if (mode != 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0);
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}
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if (xlen == 32) {
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oi = make_memop_idx(MO_LEUL, mmu_index);
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t0 = base + (index << 2);
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target = cpu_ldl_code_mmu(env, t0, oi, 0);
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} else {
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oi = make_memop_idx(MO_LEUQ, mmu_index);
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t0 = base + (index << 3);
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target = cpu_ldq_code_mmu(env, t0, oi, 0);
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}
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return target & ~0x1;
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}
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