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The POWER9 Processor User's Manual, section 4.9.4, specifies that POWER9 ignores PTCR[PATS] and only supports a 64 KiB partition table. Use an effective PATS value of 4 on POWER9; other processors keep the existing ISA v3.0 interpretation. The PSI model now exposes POWER9 IRQ level and pending status registers, and keeps both updated while delivering through the existing XIVE LSI source. This lets guests that select the POWER9 PSI LSI IRQ method continue to receive LPC interrupts. The blast radius is probably minimal: the PTCR change is limited to POWER9, while the PSI change only touches POWER9 PSI state and reuses the existing delivery path. Acked-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Kirill A. Korinsky <kirill@korins.ky> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260719145559.94342-1-kirill@korins.ky Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>