Philippe Mathieu-Daudé 2368ea9744 accel/tcg: Move cpu_loop_exit_*() out of 'exec/cpu-common.h' ...

Move the following TCG-specific cpu_loop_exit_*() declarations
out of the generic "exec/cpu-common.h" header, to the recently
created "accel/tcg/cpu-loop.h" one, documenting them:

 - cpu_loop_exit_noexc()
 - cpu_loop_exit_atomic()
 - cpu_loop_exit_restore()
 - cpu_loop_exit()

Include "accel/tcg/cpu-loop.h" where appropriate.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260617171438.75914-11-philmd@oss.qualcomm.com>

2026-06-18 14:27:21 +02:00

..

insn_trans

target/riscv: Initialize DisasContext::mo_endian once

2026-06-16 13:38:50 +10:00

kvm

target/riscv: Move CSR declarations to separate csr.h header

2026-06-15 13:10:15 +10:00

tcg

target/riscv: Add standard B extension implied rule

2026-06-16 13:58:37 +10:00

arch_dump.c

include: Rename sysemu/ -> system/

2024-12-20 17:44:56 +01:00

bitmanip_helper.c

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

common-semi-target.c

include/semihosting/common-semi: extract common_semi API

2025-09-26 09:55:19 +01:00

cpu_bits.h

target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks

2026-05-27 11:50:12 +02:00

cpu_cfg_fields.h.inc

target/riscv: Add big-endian CPU configuration field and reset logic

2026-06-16 13:50:25 +10:00

cpu_cfg.h

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

cpu_helper.c

accel/tcg: Move cpu_loop_exit_*() out of 'exec/cpu-common.h'

2026-06-18 14:27:21 +02:00

cpu_user.h

target/riscv: zicfilp lpad impl and branch tracking

2024-10-30 11:22:08 +10:00

cpu_vendorid.h

target/riscv: tt-ascalon: Add Tenstorrent mvendorid

2026-04-29 13:38:13 +10:00

cpu-param.h

exec: Drop TARGET_PHYS_ADDR_SPACE_BITS

2026-02-25 23:46:04 +01:00

cpu-qom.h

target/riscv: add thead-c908 cpu support

2026-06-16 20:01:11 +10:00

cpu.c

target/riscv: add thead-c908 cpu support

2026-06-16 20:01:11 +10:00

cpu.h

target/riscv: Set mstatus.FS dirty when scalar FP raises exceptions

2026-06-16 14:13:24 +10:00

crypto_helper.c

include: Remove 'exec/exec-all.h'

2025-04-30 12:45:05 -07:00

csr.c

accel/tcg: Move cpu_unwind_state_data() out of 'exec/cpu-common.h'

2026-06-18 14:27:21 +02:00

csr.h

target/riscv: Make pmp.h target_ulong agnostic

2026-06-15 13:10:15 +10:00

debug.c

target/riscv: Move debug.h include away from cpu.h

2026-06-15 13:10:15 +10:00

debug.h

target/riscv: Move debug.h include away from cpu.h

2026-06-15 13:10:15 +10:00

fpu_helper.c

target/riscv: Set mstatus.FS dirty when scalar FP raises exceptions

2026-06-16 14:13:24 +10:00

gdbstub.c

target/riscv: Move CSR declarations to separate csr.h header

2026-06-15 13:10:15 +10:00

helper.h

target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f

2026-05-22 09:45:46 +10:00

insn16.decode

target/riscv: Add Zilsd and Zclsd extension support

2026-01-09 15:01:10 +10:00

insn32.decode

disas/riscv.c: add 'cbo' insns to disassembler

2026-06-15 13:10:14 +10:00

instmap.h

target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

2022-09-07 09:18:32 +02:00

internals.h

target/riscv: Implement runtime data endianness via MSTATUS bits

2026-06-16 13:40:38 +10:00

Kconfig

target/riscv/cpu_helper: Fix linking problem with semihosting disabled

2024-10-02 15:11:51 +10:00

m128_helper.c

include: Remove 'exec/exec-all.h'

2025-04-30 12:45:05 -07:00

machine.c

target/riscv: Make pmp.h target_ulong agnostic

2026-06-15 13:10:15 +10:00

meson.build

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

mips_csr.c

target/riscv: Move CSR declarations to separate csr.h header

2026-06-15 13:10:15 +10:00

monitor.c

target/riscv: Move CSR declarations to separate csr.h header

2026-06-15 13:10:15 +10:00

op_helper.c

accel/tcg: Move cpu_loop_exit_*() out of 'exec/cpu-common.h'

2026-06-18 14:27:21 +02:00

pmp.c

target/riscv: Make pmp.h target_ulong agnostic

2026-06-15 13:10:15 +10:00

pmp.h

target/riscv: Fix pmp.h/cpu.h circular inclusion

2026-06-15 13:10:15 +10:00

pmu.c

target/riscv: Fix size of priv

2026-06-15 13:10:15 +10:00

pmu.h

target/riscv: Fix size of priv

2026-06-15 13:10:15 +10:00

riscv-qmp-cmds.c

target/riscv: Move CSR declarations to separate csr.h header

2026-06-15 13:10:15 +10:00

sbi_ecall_interface.h

target/riscv/kvm: implement SBI debug console (DBCN) calls

2024-06-03 11:12:11 +10:00

th_csr.c

target/riscv: add thead-c908 cpu support

2026-06-16 20:01:11 +10:00

time_helper.c

target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

2025-07-04 21:09:48 +10:00

time_helper.h

target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

2025-07-04 21:09:48 +10:00

trace-events

target/riscv: add trace in riscv_raise_exception()

2025-01-19 09:44:34 +10:00

trace.h

trace: switch position of headers to what Meson requires

2020-08-21 06:18:24 -04:00

translate.c

target/riscv: Implement runtime data endianness via MSTATUS bits

2026-06-16 13:40:38 +10:00

vcrypto_helper.c

include: Remove 'exec/exec-all.h'

2025-04-30 12:45:05 -07:00

vector_helper.c

target/riscv: rvv: Set mstatus.FS dirty when vector FP raises exceptions

2026-06-16 14:15:11 +10:00

vector_internals.c

target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter

2025-03-19 16:39:00 +10:00

vector_internals.h

include: move hw/registerfields.h to hw/core/

2025-12-27 10:11:08 +01:00

xlrbr.decode

target/riscv: add draft RISC-V Zbr ext as xbr0p93

2026-04-29 11:41:00 +10:00

xmips.decode

target/riscv: Add Xmipslsp instructions

2026-01-09 15:11:43 +10:00

xthead.decode

RISC-V: Adding XTheadFmv ISA extension

2023-02-07 08:19:23 +10:00

XVentanaCondOps.decode

target/riscv: Add XVentanaCondOps custom extension

2022-02-16 12:24:18 +10:00

zce_helper.c

target/riscv: Inline cpu_ld[lq]_code() calls

2026-02-03 14:57:33 +01:00