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750d25fc66
Defines TargetInfo for 32- and 64-bit riscv binaries. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-6-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
27 lines
703 B
C
27 lines
703 B
C
/*
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* QEMU binary/target API (qemu-system-riscv32)
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*
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* Copyright (c) rev.ng Labs Srl.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/target-info-impl.h"
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#include "qemu/target-info-init.h"
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#include "hw/riscv/machines-qom.h"
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#include "target/riscv/cpu-qom.h"
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#include "target/riscv/cpu-param.h"
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static const TargetInfo target_info_riscv32_system = {
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.target_name = "riscv32",
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.target_arch = SYS_EMU_TARGET_RISCV32,
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.long_bits = 32,
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.cpu_type = TYPE_RISCV_CPU,
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.machine_typename = TYPE_TARGET_RISCV32_MACHINE,
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.endianness = ENDIAN_MODE_LITTLE,
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.page_bits_init = TARGET_PAGE_BITS,
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};
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target_info_init(target_info_riscv32_system)
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