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target-arm queue: * hw/timer/mss_timer: Remove dead code in timer_write() * OMAP: Remove various pieces of dead code * target/arm: Set debug in attrs in translate_for_debug() * target/arm/ptw: Flip sense of get_phys_addr_* return values * tests/functional/aarch64: Bump up timeout on vbsa * target/arm: Fix minor FEAT_AFP corner case bugs * target/arm: Implement FEAT_FAMINMAX * target/arm: Implement FEAT_FPMR * target/arm: Some initial patches towards other FP8 features # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmoVrdcZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nJnEACJLdcU+Q+5EoGw+PT16tyB # anoeeMdjR8h7lGtOOfclaVwno+UzzfKEnqX5Y1MXiKpD+QcuJ/VNy431Pj0pgEiF # BOqWVLiF7jJsxHzxJ5y+OniHwoDvyZKNKv7nbgoHJY2LSUZlIA5plgr1Pj27NA4S # KFWgBIWu3uJlx7t9epUl9qbmSSHj54zXDt8N7tGhitR4be/vEjRnE/IIHbtQ0jhg # 3A68nBchBXHawjeghCmWFqh8zFlqNo9oFZoaE4/oe3qmCesh1Pg5eQ1RRvjSY9VJ # uW3m/6oLY5v5KwV2UY5etLHvWPrIjzIzkv7gnOKF2H+3yygEhSzBJDlYViSHVwS+ # pGTaW8LvSFCkhnBocN5VELC7V0XJDxlCLoaOrBYUY/wOt7tvC2qWzson+siTaiLT # VfJoRkAkf5YasK78HHfsfxdz95X3sqLR1Ks6uuVq6cH+0vdLxJ9ac8c8lu/TjwLm # qFfHoo5ryQFryRyKqUhS/TQA3Bx5qHvq1uDMu2o3BrFSzU6Rj4nR01LgrEdVacp+ # w8KjAISu7RJVwQ64u3QkP+RB5HbaLRln4FeOl4GDK4WxABKrgjkFjVwSStNVOjzQ # 7kvT48wFdQ/Mv6IL9tUPJzGhqJvrevOrM+QzbInmyzbCbcWuK0+dI+yVBf6w5AhE # a1q5vtYSMBY7a6H2WeDuBw== # =Zmy0 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 May 2026 10:27:35 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu: (54 commits) target/arm: Move vectors_overlap to vec_internal.h target/arm: Split vector-type.h from cpu.h target/arm: Implement FSCALE for SME target/arm: Implement FSCALE for AdvSIMD target/arm: Add isar_feature_aa64_f8cvt target/arm: Implement ID_AA64FPFR0 target/arm: Enable FEAT_FPMR for -cpu max linux-user/aarch64: Implement FPMR signal frames target/arm: Dump FPMR when present tests/functional/aarch64/rme: update images to support FEAT_FP8 target/arm: Trap direct acceses to FPMR target/arm: Add FPMR_EL to TBFLAGS target/arm: Clear FPMR on ResetSVEState target/arm: Enable EnFPM bits for FEAT_FPMR target/arm: Update SCTLR bits for FEAT_FPMR target/arm: Introduce FPMR target/arm: Update HCRX bits for Arm ARM M.a.a target/arm: Update SCR bits for Arm ARM M.a.a target/arm: Enable FEAT_FAMINMAX for -cpu max target/arm: Implement FEAT_FAMINMAX for SVE ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>