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9e65902904
We transform target/{arm,riscv}/common-semi-target.h headers to proper
compilation units, and use them in arm-compat-semi.c.
This way, we can include only the declaration header (which is target
agnostic), and selectively link the appropriate implementation based on
current target.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250822150058.18692-8-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20250922093711.2768983-11-alex.bennee@linaro.org>
50 lines
1.0 KiB
C
50 lines
1.0 KiB
C
/*
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* Target-specific parts of semihosting/arm-compat-semi.c.
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*
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* Copyright (c) 2005, 2007 CodeSourcery.
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* Copyright (c) 2019, 2022 Linaro
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* Copyright © 2020 by Keith Packard <keithp@keithp.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "semihosting/common-semi.h"
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uint64_t common_semi_arg(CPUState *cs, int argno)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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return env->gpr[xA0 + argno];
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}
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void common_semi_set_ret(CPUState *cs, uint64_t ret)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->gpr[xA0] = ret;
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}
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bool is_64bit_semihosting(CPUArchState *env)
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{
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return riscv_cpu_mxl(env) != MXL_RV32;
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}
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bool common_semi_sys_exit_is_extended(CPUState *cs)
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{
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return is_64bit_semihosting(cpu_env(cs));
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}
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uint64_t common_semi_stack_bottom(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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return env->gpr[xSP];
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}
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bool common_semi_has_synccache(CPUArchState *env)
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{
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return true;
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}
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