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a59157f98f
RISC-V PR for 11.1 * Fix IMSIC CSR write and add tests * Parametrise debug trigger number * Add 'svbare' satp-mode * Fix RINTC PLIC context ID for KVM * Avoid abort when reading vtype before env->xl is set * Skip reset for KVM irqchip * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE * More FDT cleanups (PLIC) * Make FCTL.BE in IOMMU read only 0 * Check DC.TC reserved bits in IOMMU * Apply UXL WARL handling to vsstatus * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU * Set RISCV_IOMMU_FQ_HDR_PV appropriately * Fix MSI MRIF IOMMU interrupt-pending offset * Report QEMU CPU archid as 42 * Check PMP before updating PTE * Add the Tenstorrent Atlantis machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmpE6SoACgkQr3yVEwxT # gBOxNQ//bI4BvnT65Kd2UNMgtAwwPPcehpsyPzC2S3BcflniXQL+fV6sQ7IreKta # 6dclp/v5v+yhbB4bd/E1s/UPOF3YD4A9noUFifIhymBkafmqA4YRNsvPByeGiSD8 # xVkHhX5qUT9NW5wKnivEDjO8mndBMRm5YEXQ6uT5ulUsZr3Ir8wPOCJITZ8ZqKwb # 6dbbXStf1aTIBzu53KaNhNpi9DQqKV5UeV7CiSuhuwWU0qmVg1RAZMg9X3oB80rE # WpWqH0rg9Z0Cn+3XL+oKSzbLD5SrrTV+Ohq+K8zT2rEk+hIXOE3shAPm2xfTT9Q2 # g65nBOf2UmNWeHlvn3XC2LtmIWq10/A78ogGgm4XwHx8TXIeA2KIKboyS8T37XAb # NwUllq9LRtfDVtDevpiTn6t7Oa7TC8zrxDJTT1rg/p+3D6MdfkonifwJJgVAwfuG # NF7R2iePKPQliWr1hi6W+ghzQMRFXgNBwUNOL39/BQguy5IqvNmSk6ovhl8IFocf # aXGh9U35DqgrsUvMa/7Fgf4uI2QNhERBGJrHfL0SPZ82sKb5CTrMw9URwg0DFnEF # 8v/zQ9xL4eF0uZn0OtaNlLXRCblDxcHSgecwix9Vip5toFIc1P8ar9FX98Zd/H5l # UD/a3ENtiwb6hnKhZ+45iM/NIFJeUK7A0944VnQzx00tA06wJLw= # =a4hl # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Jul 2026 12:17:14 CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits) hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 hw/riscv/atlantis: Add some i2c peripherals hw/riscv/atlantis: Integrate i2c controllers hw/i2c: Add DesignWare I2C Controller tests/functional/riscv64: Add tt-atlantis tests hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr hw/riscv: Add Tenstorrent Atlantis machine target/riscv: tt-ascalon: Enable Zkr extension hw/riscv/aia: Configure stride for the M-mode IMSIC hw/riscv/aia: Provide number of irq sources hw/riscv/virt: Move AIA initialisation to helper file hw/riscv/boot: Account for discontiguous memory when loading firmware hw/riscv/boot: Describe discontiguous memory in boot_info target/riscv: Check PMP before updating PTE target/riscv: Report QEMU CPU archid as 42 hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set target/riscv: Apply UXL WARL handling to vsstatus hw/riscv/riscv-iommu: check DC.TC reserved bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>