Aurelien Jarno afa88c3ae5 target-mips: add Loongson support prefetch ...

Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

2010-07-01 23:45:28 +02:00

..

cpu.h

target-mips: add microMIPS exception handler support

2010-06-09 16:10:51 +02:00

exec.h

kill regs_to_env and env_to_regs

2010-01-19 16:31:02 -06:00

helper.c

target-mips: add microMIPS exception handler support

2010-06-09 16:10:51 +02:00

helper.h

target-mips: microMIPS ASE support

2010-06-09 16:10:50 +02:00

machine.c

target-mips: rename CP0_LLAddr into lladdr

2009-11-22 14:12:13 +01:00

mips-defs.h

MIPS: Initial support of fulong mini pc (CPU definition)

2010-06-29 23:07:52 +02:00

op_helper.c

target-mips: microMIPS ASE support

2010-06-09 16:10:50 +02:00

TODO

target-mips: add copyright notice for mips16 work

2009-12-13 20:20:20 +01:00

translate_init.c

MIPS: Initial support of fulong mini pc (CPU definition)

2010-06-29 23:07:52 +02:00

translate.c

target-mips: add Loongson support prefetch

2010-07-01 23:45:28 +02:00