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Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV with a property RISCVIOMMUState::pas_bits that gets written to the capabilities field upon device realization. This write needs to happen at realize-time to ensure the property has been set. For the virt machine and sysbus device, pas_bits is set by virt_machine_init() to either 34 or 56 bits, retaining previous behaviour. However, for the PCI device we do not have access to the CPU state, and instead use the maximum riscv64 value of 56 bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Message-ID: <20260218-phys_addr-v6-6-a603bf363218@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>