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20df4ef1c9
A conflict exists when any GPR is written by multiple instructions and at least one write is unconditional. This catches (1) two unconditional writes to the same GPR and (2) an unconditional write combined with a predicated write. Add HEX_CAUSE_REG_WRITE_CONFLICT and map it to SIGILL. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2696 Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "user/cpu_loop.h"
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#include "signal-common.h"
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#include "internal.h"
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void cpu_loop(CPUHexagonState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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target_ulong syscallnum;
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target_ulong ret;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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qemu_process_cpu_events(cs);
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switch (trapnr) {
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case HEX_EVENT_TRAP0:
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syscallnum = env->gpr[6];
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env->gpr[HEX_REG_PC] += 4;
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ret = do_syscall(env,
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syscallnum,
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env->gpr[0],
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env->gpr[1],
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env->gpr[2],
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env->gpr[3],
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env->gpr[4],
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env->gpr[5],
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0, 0);
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if (ret == -QEMU_ERESTARTSYS) {
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env->gpr[HEX_REG_PC] -= 4;
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} else if (ret != -QEMU_ESIGRETURN) {
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env->gpr[0] = ret;
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}
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break;
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case HEX_CAUSE_PC_NOT_ALIGNED:
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force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
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env->gpr[HEX_REG_R31]);
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break;
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case HEX_CAUSE_INVALID_PACKET:
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case HEX_CAUSE_REG_WRITE_CONFLICT:
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC,
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env->gpr[HEX_REG_PC]);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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case EXCP_DEBUG:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, 0);
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break;
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default:
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EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
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trapnr);
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exit(EXIT_FAILURE);
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}
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process_pending_signals(env);
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}
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}
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void init_main_thread(CPUState *cs, struct image_info *info)
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{
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CPUArchState *env = cpu_env(cs);
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env->gpr[HEX_REG_PC] = info->entry;
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env->gpr[HEX_REG_SP] = info->start_stack;
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env->gpr[HEX_REG_USR] = 0x56000;
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}
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