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cbb724e0bd3fde72f0d68abceb79c6d94de08e01
qemu/target/riscv
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Philippe Mathieu-Daudé de32a75647 target/riscv: Remove unnecessary target_ulong type uses 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260219191955.83815-29-philmd@linaro.org>
2026-02-26 00:02:14 +01:00
..
insn_trans
target/riscv: Drop TCG_TARGET_REG_BITS test
2026-01-17 10:46:18 +11:00
kvm
error: Use error_setg_errno() to improve error messages
2026-01-08 07:49:23 +01:00
tcg
target/riscv: Add Zilsd and Zclsd extension support
2026-01-09 15:01:10 +10:00
arch_dump.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
bitmanip_helper.c
codebase: prepare to remove cpu.h from exec/exec-all.h
2025-04-23 13:52:25 -07:00
common-semi-target.c
include/semihosting/common-semi: extract common_semi API
2025-09-26 09:55:19 +01:00
cpu_bits.h
target: riscv: Add Svrsw60t59b extension support
2025-07-04 21:09:49 +10:00
cpu_cfg_fields.h.inc
target/riscv: Add Xmipslsp instructions
2026-01-09 15:11:43 +10:00
cpu_cfg.h
target/riscv: Add Xmipslsp instructions
2026-01-09 15:11:43 +10:00
cpu_helper.c
target/riscv: Fix size of mhartid
2026-01-09 15:01:09 +10:00
cpu_user.h
target/riscv: zicfilp lpad impl and branch tracking
2024-10-30 11:22:08 +10:00
cpu_vendorid.h
target/riscv: Add MIPS P8700 CPU
2026-01-09 15:10:19 +10:00
cpu-param.h
exec: Drop TARGET_PHYS_ADDR_SPACE_BITS
2026-02-25 23:46:04 +01:00
cpu-qom.h
target/riscv: Add MIPS P8700 CPU
2026-01-09 15:10:19 +10:00
cpu.c
disas: Have disas_set_info() take a const CPUState
2026-02-03 14:57:34 +01:00
cpu.h
target/riscv: Add MIPS P8700 CSRs
2026-01-09 15:10:46 +10:00
crypto_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
csr.c
misc: Clean up includes
2026-01-22 11:23:31 +00:00
debug.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
debug.h
target/riscv: Add textra matching condition for the triggers
2024-10-02 15:11:51 +10:00
fpu_helper.c
target/riscv: Fix fcvt.s.bf16 NaN box checking
2025-07-04 21:09:48 +10:00
gdbstub.c
target/riscv: Remove unnecessary target_ulong type uses
2026-02-26 00:02:14 +01:00
helper.h
target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64
2025-10-03 13:15:14 +10:00
insn16.decode
target/riscv: Add Zilsd and Zclsd extension support
2026-01-09 15:01:10 +10:00
insn32.decode
Add RISCV ZALASR extension
2026-01-09 15:09:49 +10:00
instmap.h
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
2022-09-07 09:18:32 +02:00
internals.h
include: move hw/registerfields.h to hw/core/
2025-12-27 10:11:08 +01:00
Kconfig
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-10-02 15:11:51 +10:00
m128_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
machine.c
target/riscv: Combine mhpmcounter and mhpmcounterh
2026-01-09 15:01:10 +10:00
meson.build
target/riscv: Add mips.ccmov instruction
2026-01-09 15:11:13 +10:00
mips_csr.c
target/riscv: Add MIPS P8700 CSRs
2026-01-09 15:10:46 +10:00
monitor.c
target/riscv: Remove empty target_monitor_defs() symbol
2026-02-26 00:02:14 +01:00
op_helper.c
target/riscv: Introduce mo_endian_env() helper
2025-10-24 09:24:08 +10:00
pmp.c
target/riscv: Make PMP CSRs conform to WARL constraints
2025-10-24 09:24:08 +10:00
pmp.h
target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0
2025-01-19 09:44:34 +10:00
pmu.c
target/riscv: Combine mhpmcounter and mhpmcounterh
2026-01-09 15:01:10 +10:00
pmu.h
target/riscv: More accurately model priv mode filtering.
2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c
target/riscv: Extract monitor-related code to monitor.c
2026-02-25 23:46:04 +01:00
sbi_ecall_interface.h
target/riscv/kvm: implement SBI debug console (DBCN) calls
2024-06-03 11:12:11 +10:00
th_csr.c
target/riscv: generalize custom CSR functionality
2025-05-20 08:18:53 +02:00
time_helper.c
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
2025-07-04 21:09:48 +10:00
time_helper.h
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
2025-07-04 21:09:48 +10:00
trace-events
target/riscv: add trace in riscv_raise_exception()
2025-01-19 09:44:34 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
target/riscv: Inline translator_ld[uw,l,q]() calls
2026-02-03 14:57:33 +01:00
vcrypto_helper.c
include: Remove 'exec/exec-all.h'
2025-04-30 12:45:05 -07:00
vector_helper.c
target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector
2026-01-22 10:41:37 +01:00
vector_internals.c
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
2025-03-19 16:39:00 +10:00
vector_internals.h
include: move hw/registerfields.h to hw/core/
2025-12-27 10:11:08 +01:00
xmips.decode
target/riscv: Add Xmipslsp instructions
2026-01-09 15:11:43 +10:00
xthead.decode
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00
zce_helper.c
target/riscv: Inline cpu_ld[lq]_code() calls
2026-02-03 14:57:33 +01:00