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target-arm queue: * hw/timer/imx_epit: Replace DPRINTF with trace events target/arm: Enable SCTLR_EL1.EnFPM for user-only target/arm: Implement FEAT_SME_F8F32 target/arm: Implement FEAT_SSVE_AES target/arm: Implement FEAT_SME_F8F16 target/arm: GICv5: Fix some minor bugs target/arm: Add GPC3 granule bypass windows target/arm: Fix some minor timer related bugs hw/arm/sabrelite: Add FlexCAN emulation docs/system: add FEAT_ECV_POFF to the emulation list docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmpCXaQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nfkEACJkoMzHDyHcAiRdO8fK4o6 # zHP3f42UOnXTbX//Yga0PpxScWfvD8XbbOSeJRvpjuxl8nP8QF4/rF4b+atMy9Vl # MH0r/CWl9fZwQOSmjOLzgRGzXx0j9RPPpB/7eYTnKYImfOaEEaGvW4JqoBRE2Nbo # x5PaQjaqFQi76uGAJvALPgAPCgaK1DGbNDSRuH4RM7auLBWmSaoxdidiTDSBUqY0 # xsI/lU7t+/LLWirjP/QhM4mbxEc2DjENbguRHYlOqe5aHc6KdSmNj2B4/hTfyDON # c6APaAAPfCy3duL3JsvmwRZ8YM7zoUFEHysLjRxLWyiFfXZUIXPSMZaGpz88iyDV # Cbraw24K5tVVNvwQTKOpHYCnjNb4dZj1Zt/jdGIu16LQ8nsKgX2EJ6oh6lI85Q6n # d3Jbq+iLOy2r2r4CRTMIJYKZ2Bikkmyr+wZGO18nttnTVpWNzWVZtq4cutygr5vb # 0+5Lmr7YeYsdmIc1tpcJmlfmmo7dW987HyzK3/B65gPXV64w+a3eALRLPkMGevTT # MhG48151NEovHxfKqzsOMIixnPUKGPtAUbeKy/Ywv2ezKUmER19h/7nJ0lsa32pl # HYctGj4QeK4VjOO8E1q44ZIionhZFt+RHXBxxbiBzQBns/ryFBOQFEA3WzKi7rnd # a0v1M+AAK/UxmCjV7Sl0WA== # =OvGk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jun 2026 13:57:24 CEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu: (54 commits) docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV target/arm: Enable FEAT_SME_F8F16 for -cpu max target/arm: Implement FVDOT (FP8 to FP16) target/arm: Rename FVDOT pattern target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16) target/arm: Implement FDOT (multiple and indexed, FP8 to FP16) target/arm: Implement FDOT (multiple, multiple and single, FP8 to FP16) target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16) target/arm: Implement FMLAL (multiple, multiple and single, FP8 to FP16) target/arm: Rename SME FMLAL/FMLSL patterns target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16 docs/system: add FEAT_ECV_POFF to the emulation list target/arm: trigger timer recalc on HCR:(E2H|TGE) changes target/arm: gate check on scr_el3 behind ARM_FEATURE_EL3 check target/arm: trigger timer recalc on SCR:ECVEN change target/arm: trigger timer recalculation when toggling CNTHCTL:ECV target/arm: split evaluation of CNTHCTL timer IRQ masks docs/arm/sabrelite: Mention FlexCAN support tests: Add qtests for FlexCAN hw/arm: Plug FlexCAN into FSL_IMX6 and Sabrelite ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>