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282771e1f9
RISC-V PR for 11.1. * Use standard EN_PRI bit for PRI IOMMU * Add draft RISC-V Zbr ext as xbr0p93 * Forbid to use legacy native endianness API * Fix irq_overflow_left residual value bug in IOMMU * Add IPSR.PMIP RW1C support to IOMMU * Use kvm timer frequency when kvm enabled * Fix stale ptshift and base on page walk restart * Fix heap OOB in ACLINT MTIMER multi-socket * Reject RISC-V HTIF invalid signature ranges * Fix RV32 henvcfg/stateen CSR handling * Add Zvfbfa extension support * Allow fractional LMUL on vector SHA instructions * Add Tenstorrent mvendorid * Warn if a ELF format file is loaded as a binary * Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer * Mask xepc[0] only when Zc* extension is enabled * Generate access fault if sc comparison fails * Don't OR mip.SEIP when mvien is one * Use ELEN for Fractional LMUL check * Fix Zjpm implementation * Handle mask/source overlap of vector reduction instructions # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmnxjOkACgkQr3yVEwxT # gBMf6Q/+IdCh9/rzqJFyBcHxkbQGMncGzBsmLHmeCIgUc7gPxF8Cw6zFbJ3p2H3m # ry4pnrqp8juKlDfuDcQyXgoQSWJ5MqkrQZaxUUomEhZPoJr3XrWXcp9nVPAOOtni # WQR/AW0rsm97ujaAN/OSQKUFOfUVzRSOrSZg0xSg3fmYTia7CEKVKByQnfNlKLvk # 6RRax8Dlcmmn2Q9AXWV5oaEH8ZDorC6GRN2p805LLzdEWmkY5wMKaHAnTXs8qErm # wK4E+CWmFW2f5h1Mg0MvuV5Ko6TDFD7wghSM/HV7Aykdvwg2bO2MUmEt0zMQwtMU # OOx/UihFDcPBDLjnrVTsLEf02ol98W6gkqAxhpiGez5PGzfYX7xNMFHHj6RqA/dC # kThR5CfThVY+Daw9F26b8kovq/xlaeM6nZM5L4qtMpZbojZbZ414H15prBlJoYF9 # R1amO14+VNuZBrPIXFOLbPk8T5DmM8Km9V/oaV6Ra/vkSF43tmiqrV/s4+NbBIZB # H42JDlruats9kTFeMggZS4VVkgkNgelM4cvvfK8KAhp6sdmub/cPxlZcYsnuOuD3 # lJEBWO3bDNpEHsHCLrwYVlS3dZQXWo+KifHElK8lMOW3b/93rjlzgLRERvdaVxpb # NlCOjGwGxfb/Z7r1ylcrbK2DONP0kuoZDpVfacqZ8UXbxnyvosg= # =oT5a # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 Apr 2026 00:45:29 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260429-1' of https://github.com/alistair23/qemu: (51 commits) target/riscv: rvv: Handle mask/source overlap of vector reduction instructions target/riscv: Fix pointer masking translation mode check bug target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() target/riscv: Fix pointer masking for virtual-machine load/store insns target/riscv: Fix pointer masking PMM field selection logic target/riscv: Add a helper to return the current effective priv mode target/riscv: fix address masking target/riscv: Use ELEN for Fractional LMUL check target/riscv: Don't OR mip.SEIP when mvien is one target/riscv: Generate access fault if sc comparison fails target/riscv: Mask xepc[0] only when Zc* extension is enabled target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer target/riscv: fix RV32 stateen CSR handling hw/riscv/boot: Warn if a ELF format file is loaded as a binary target/riscv: tt-ascalon: Add Tenstorrent mvendorid target/riscv: rvv: Allow fractional LMUL on vector SHA instructions target/riscv: Expose Zvfbfa extension as a cpu property target/riscv: rvv: Support Zvfbfa vector bf16 operations target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension target/riscv: Introduce altfmt into DisasContext ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>