Compilers used to compile the master prom

compilers/HT-XA/BIN/HPDXA.INI

@@ -0,0 +1,27 @@
+[HPDXA]
+Project=none
+Curfile=none
+Tabsize=8
+File0=C:\WORK\5230_SPG\SYSTEM.C 1 1
+File1=C:\WORK\5230_SPG\SYNC.C 1 1
+File2=C:\WORK\5230_SPG\LOCK.C 1 1
+File3=C:\WORK\5230_SPG\FIEL.C 1 1
+File4=C:\WORK\5230_SPG\LINE.C 1 1
+File5=C:\WORK\5230_SPG\SERI1.C 1 1
+File6=C:\WORK\5230_SPG\TABKORG.C 1 1
+File7=C:\WORK\5230_SPG\TABKORM.C 1 1
+Ucnam0=
+Ucmd0=
+Ucnam1=
+Ucmd1=
+Ucnam2=
+Ucmd2=
+Ucnam3=
+Ucmd3=
+SavedTemp=
+Autosave=0
+Warnlevel=0
+[WINDOWS]
+MOUSE=8,4098,0,1
+SOUND=On
+CLOCK=On

compilers/HT-XA/BIN/PATCH.LVL

@@ -0,0 +1 @@
+XAV7.72 patchlevel 1

compilers/HT-XA/BIN/XX/HPDXA.INI

@@ -0,0 +1,148 @@
+[HPDXA]
+Project=C:\WORK\5210\SYNC\SYNC.PRJ
+Curfile=C:\CXA\WORK\JK_SPG\SYNC.C 33 1
+Tabsize=2
+#
+#	Menu bar clock enable: 0 = off, non-zero = on
+#
+Clock=1
+#
+#	sound enable: 0 = off, non-zero = on
+#
+Sound=1
+#
+Ucnam0=
+Ucmd0=
+Ucnam1=
+Ucmd1=
+Ucnam2=
+Ucmd2=
+Ucnam3=
+Ucmd3=
+SavedTemp=
+Autosave=0
+Warnlevel=0
+File0=C:\CXA\WORK\JK_SPG\LOCK.C 136 1
+File1=C:\CXA\WORK\JK_SPG\SYNC.H 49 1
+File2=C:\WORK\5210\SYNC\SYSTEM.C 1 1
+File3=C:\WORK\5210\SYNC\SYNC.C 1 1
+File4=C:\WORK\5210\SYNC\LOCK.C 1 1
+File5=C:\WORK\5210\SYNC\FIEL.C 1 1
+File6=C:\WORK\5210\SYNC\LINE.C 1 1
+File7=C:\WORK\5210\SYNC\SERI1.C 1 1
+[WINDOWS]
+#
+#	The SCREEN=rows,lines value is used to select any of the "standard"
+#	EGA or VGA text modes.  This value is only used if EGA or VGA are
+#	detected.  Useful combinations are:
+#
+#		EGA:	25,350 or 43,350  (these also work on VGA)
+#		VGA:	25,400, 28,400 or 50,400
+#
+#	The SCREEN= value will not set a lower resolution mode than is
+#	already in use.  Eg. SCREEN=25,400 will not set 25 lines if a
+#	50 line screen is already selected using the DOS MODE command.
+#	The 28 rows by 400 scan lines mode is very nice on most VGA displays.
+#
+SCREEN=28,400
+#
+MOUSE=50,50,0,1
+SOUND=On
+CLOCK=On
+[COLOURS]
+#
+#	colour settings:
+#
+#	Remove the # before any line to set the colours for the specifed
+#	window.  In each colour group, the first value is the foreground
+#	colour, the second is the background colour.  The attribute names
+#	for most windows are:
+#
+#	normal:		normal text colour
+#	bright:		bright/highlighted text colour 
+#	inverse:	inverse text colour
+#	frame:		window frame colour
+#	title:		window title colour
+#	button:		colour for any buttons in window
+#
+#	If just the "normal" colour for a window is specified, the
+#	settings of "bright", "inverse", "frame" and "title" will be
+#	extrapolated from the "normal" colour.
+#
+#	Valid colours: foreground: 0-15, background: 0-7
+#
+#	0=black		1=blue		2=green		3=cyan
+#	4=red		5=magenta	6=brown		7=white
+#	8=grey		9=bright blue	10=bright green	11=bright cyan
+#	12=bright red	13=br. magenta	14=yellow	15=bright white
+#
+#	The settings below create a horrible "neon" colour scheme.
+#
+#Editor=normal:7,1 bright:0,3 button:1,7 hilite:14,0
+#Clipboard=normal:7,0 bright:14,0
+#Table_help=normal:14,0 bright:15,0
+#Compdial=normal:7,4 bright:7,0 frame:6,4
+#Map_window=normal:0,5
+#Help_window=normal:14,0 bright:15,0 inverse:4,7
+#Ascii_window=normal:2,0 button:4,7 high:3,0
+#Calculator=normal:7,0
+#Warndial=normal:7,4
+#Msg_window=normal:15,6
+#
+#	Set C_colours=1 to enable C colour coding, C_colours=0 to disable
+#
+C_colours=1
+#
+#	The settings below define the colours used by the editor
+#	when displaying colour coded C source.  The editor breaks
+#	C code into "language elements" named as follows:
+#
+#	C_wspace:	White space - foreground colour affects cursor
+#	C_number:	Octal, decimal and hexadecimal numbers
+#	C_alpha:	Alphanumeric variable, macro and function names
+#	C_punct:	Punctuation characters, etc.
+#	C_keyword:	C keywords and variable types: e.g. int, static, etc.
+#	C_brace:	Open and close braces: { }
+#	C_s_quote:	Text in single quotes
+#	C_d_quote:	Text in double quotes
+#	C_comment:	Traditional C style comments: /* ... */
+#	Cpp_comment:	C++ style comments: // ...
+#	C_preprocessor:	C pre-processor directives: #blah
+#	Include_file:	Include file names
+#	Error:		Errors - anything incorrect detected by the editor
+#	Asm_code:	Inline assembler code (#asm ... #endasm)
+#	Asm_comment:	Assembler comments: ; ...
+#
+#C_wspace=7,1
+#C_number=7,1
+#C_alpha=7,1
+#C_punct=15,1
+#C_keyword=15,1
+#C_brace=11,1
+#C_s_quote=3,1
+#C_d_quote=3,1
+#C_comment=14,1
+#Cpp_comment=14,1
+#C_preprocessor=13,1
+#Include_file=2,1
+#Error=6,1
+#Asm_code=11,1
+#Asm_comment=14,1
+#
+#	The settings below may be used to create menu and menu bar
+#	colour schemes.  The following attribute values are valid:
+#
+#	Menu:	normal:		dimmed menu item, can't be selected
+#		bright:		selectable menu item
+#		inverse:	currently highlighted menu item
+#		frame:		menu frame colour
+#
+#	Menubar:
+#		normal:		menu bar normal colour
+#		inverse:	colour of half blocks around selected menu
+#		bright:		selected menu colour
+#		altkey:		alt key standard colour
+#		altdown:	alt key pressed colour
+#
+#Menu=normal:6,7 inverse:7,0 bright:0,7
+#Menubar=normal:0,7 inverse:7,0 bright:7,0 altkey:4,7 altdown:7,0

compilers/HT-XA/INCLUDE/ASSERT.H

@@ -0,0 +1,20 @@
+/*
+ *	Assertion - use liberally for debugging. Defining NDEBUG
+ *	turns assertions off.
+ *	assert(exp) where exp is non-zero does nothing, while
+ *	assert(exp) where exp evaluates to zero aborts the program
+ *	with a message like
+ *
+ *	Assertion failed: prog.c line 123: "exp"
+ *
+ */
+
+#ifndef	NDEBUG
+#ifndef	__mkstr__
+#define	__mkstr__(exp)	#exp
+#endif
+extern void	_fassert(int, char *, char *);
+#define	assert(exp)	if(!(exp)) {_fassert(__LINE__, __FILE__, __mkstr__(exp));}
+#else
+#define	assert(exp)
+#endif

compilers/HT-XA/INCLUDE/CONIO.H

@@ -0,0 +1,32 @@
+/*
+ *	Low-level console I/O functions
+ */
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef	unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+#endif	/* _STDDEF */
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	/* NULL */
+
+extern int	errno;			/* system error number */
+
+#if	!_HOSTED
+extern void	init_uart(void);
+#endif
+extern char	getch(void);
+extern char	getche(void);
+extern void	putch(char);
+extern void	ungetch(char);
+#ifdef	_MPC_
+extern bit	kbhit(void);
+#else
+extern int	kbhit(void);
+#endif
+extern char *	cgets(char *);
+extern void	cputs(const char *);

compilers/HT-XA/INCLUDE/CTYPE.H

@@ -0,0 +1,52 @@
+#if	defined(_MPC_)
+
+extern bit isalpha(char);
+extern bit isupper(char);
+extern bit islower(char);
+extern bit isdigit(char);
+extern bit isxdigit(char);
+extern bit isspace(char);
+extern bit ispunct(char);
+extern bit isalnum(char);
+extern bit isprint(char);
+extern bit isgraph(char);
+extern bit iscntrl(char);
+
+extern char	toupper(char);
+extern char	tolower(char);
+#else
+
+#define	_U	0x01
+#define	_L	0x02
+#define	_N	0x04
+#define	_S	0x08
+#define _P	0x10
+#define _C	0x20
+#define	_X	0x40
+#define	_B	0x80
+
+#ifdef	_XA_
+extern code unsigned char _ctype_[257];
+#else
+extern const unsigned char _ctype_[257];
+#endif
+
+#define	isalpha(c)	((_ctype_+1)[(unsigned char)(c)]&(_U|_L))
+#define	isupper(c)	((_ctype_+1)[(unsigned char)(c)]&_U)
+#define	islower(c)	((_ctype_+1)[(unsigned char)(c)]&_L)
+#define	isdigit(c)	((_ctype_+1)[(unsigned char)(c)]&_N)
+#define	isxdigit(c)	((_ctype_+1)[(unsigned char)(c)]&(_N|_X))
+#define	isspace(c)	((_ctype_+1)[(unsigned char)(c)]&_S)
+#define ispunct(c)	((_ctype_+1)[(unsigned char)(c)]&_P)
+#define isalnum(c)	((_ctype_+1)[(unsigned char)(c)]&(_U|_L|_N))
+#define isprint(c)	((_ctype_+1)[(unsigned char)(c)]&(_P|_U|_L|_N|_B))
+#define isgraph(c)	((_ctype_+1)[(unsigned char)(c)]&(_P|_U|_L|_N))
+#define iscntrl(c)	((_ctype_+1)[(unsigned char)(c)]&_C)
+
+extern char	toupper(int);
+extern char	tolower(int);
+#endif
+
+#define isascii(c)	(!((c)&~0x7F))
+#define toascii(c)	((c)&0x7F)
+

compilers/HT-XA/INCLUDE/ERRNO.H

@@ -0,0 +1,17 @@
+#define	EINVAL	1
+#define	ENOENT	2
+#define	NOPATH	3
+#define	EMFILE	4
+#define	EACCESS	5
+#define	EBADF	6
+#define	EMCBD	7
+#define	ENOMEM	8
+#define	EIMBA	9
+#define	EINVENV	10
+#define	ENOEXEC	11
+#define	EPERM	12
+#define	EDATA	13
+#define	EDRIVE	15
+#define	ECURDIR	16
+#define	EXDEV	17
+#define	ENFILE	18

compilers/HT-XA/INCLUDE/FLOAT.H

@@ -0,0 +1,170 @@
+/*	Characteristics of floating types */
+
+#define	DBL_RADIX	2		/* radix of exponent for a double */
+#define	DBL_ROUNDS	0		/* doubles don't round when converted to int */
+#define	FLT_RADIX	2		/* radix of float exponent */
+#define	FLT_ROUNDS	0		/* float also truncates to int */
+
+#if	defined(i8096) || defined(m6800) || defined(m6809) || defined(i8051) || \
+	defined(h8300) || defined(h8300h)|| defined(m6805)
+#define	FLT_MANT_DIG	24
+#define	FLT_EPSILON	1.19209290e-07
+#define	FLT_DIG		6
+#define	FLT_MIN_EXP	-125
+#define	FLT_MIN		1.17549435e-38
+#define	FLT_MIN_10_EXP	-37
+#define	FLT_MAX_EXP	128
+#define FLT_MAX         3.40282347e+38
+#define	FLT_MAX_10_EXP	38
+#define	DBL_MANT_DIG	24
+#define	DBL_EPSILON	1.19209290e-07
+#define	DBL_DIG		6
+#define	DBL_MIN_EXP	-125
+#define	DBL_MIN		1.17549435e-38
+#define	DBL_MIN_10_EXP	-37
+#define	DBL_MAX_EXP	128
+#define DBL_MAX         3.40282347e+38
+#define	DBL_MAX_10_EXP	38
+#endif
+
+#if	defined(_MPC_)
+	
+/* MICROCHIP PIC */
+
+#define	FLT_MANT_DIG	16
+#define	FLT_EPSILON	3.05176e-05
+#define	FLT_DIG		5
+#define	FLT_MIN_EXP	-125
+#define	FLT_MIN		1.17549435e-38
+#define	FLT_MIN_10_EXP	-37
+#define	FLT_MAX_EXP	128
+#define FLT_MAX         3.40277e+38
+#define	FLT_MAX_10_EXP	38
+#if	sizeof(double) == 4
+#define	DBL_MANT_DIG	24
+#define	DBL_EPSILON	1.19209290e-07
+#define	DBL_DIG		6
+#define	DBL_MIN_EXP	-125
+#define	DBL_MIN		1.17549435e-38
+#define	DBL_MIN_10_EXP	-37
+#define	DBL_MAX_EXP	128
+#define DBL_MAX         3.40282347e+38
+#define	DBL_MAX_10_EXP	38
+#else
+#define	DBL_MANT_DIG	FLT_MANT_DIG
+#define	DBL_EPSILON	FLT_EPSILON
+#define	DBL_DIG		FLT_DIG
+#define	DBL_MIN_EXP	FLT_MIN_EXP
+#define	DBL_MIN		FLT_MIN
+#define	DBL_MIN_10_EXP	FLT_MIN_10_EXP
+#define	DBL_MAX_EXP	FLT_MAX_EXP
+#define DBL_MAX         FLT_MAX
+#define	DBL_MAX_10_EXP	FLT_MAX_10_EXP
+#endif
+#endif
+
+#if	defined(_XA_)
+#define	FLT_MANT_DIG	24
+#define	FLT_EPSILON	1.19209290e-07
+#define	FLT_DIG		6
+#define	FLT_MIN_EXP	-125
+#define	FLT_MIN		1.17549435e-38
+#define	FLT_MIN_10_EXP	-37
+#define	FLT_MAX_EXP	128
+#define FLT_MAX         3.40282347e+38
+#define	FLT_MAX_10_EXP	38
+#define	FLT_MANT_DIG	24		/* 24 bits in mantissa */
+#if	sizeof(double) == 4
+#define	DBL_MANT_DIG	24
+#define	DBL_EPSILON	1.19209290e-07
+#define	DBL_DIG		6
+#define	DBL_MIN_EXP	-125
+#define	DBL_MIN		1.17549435e-38
+#define	DBL_MIN_10_EXP	-37
+#define	DBL_MAX_EXP	128
+#define DBL_MAX         3.40282347e+38
+#define	DBL_MAX_10_EXP	38
+#define	DBL_MANT_DIG	24		/* 24 bits in mantissa */
+#elif	__FASTDBL
+#define	DBL_MANT_DIG	48
+#define	DBL_EPSILON	2.147544363e-10
+#define	DBL_DIG		14
+#define	DBL_MIN_EXP	-16381
+#define	DBL_MIN		2.225073858507202e-1640
+#define	DBL_MIN_10_EXP	-1640
+#define	DBL_MAX_EXP	16384
+#define	DBL_MAX		1.797693134862315e+1640
+#define	DBL_MAX_10_EXP	1641
+#else
+#define	DBL_MANT_DIG	53
+#define	DBL_EPSILON	2.220446049250313e-16
+#define	DBL_DIG		15
+#define	DBL_MIN_EXP	-1021
+#define	DBL_MIN		2.225073858507202e-308
+#define	DBL_MIN_10_EXP	-307
+#define	DBL_MAX_EXP	1024
+#define	DBL_MAX		1.797693134862315e+308
+#define	DBL_MAX_10_EXP	308
+#endif
+#endif
+
+
+#if	defined(z80)
+#define	FLT_MANT_DIG	24		/* 24 bits in mantissa */
+#define	DBL_MANT_DIG	24		/* ditto for double */
+#define	DBL_MANT_DIG	24		/* ditto long double */
+#define	FLT_EPSILON	1.19209290e-07	/* smallest x, x+1.0 != 1.0 */
+#define	DBL_EPSILON	1.19209290e-07	/* smallest x, x+1.0 != 1.0 */
+#define	FLT_DIG		6		/* decimal significant digs */
+#define	DBL_DIG		6
+#define	FLT_MIN_EXP	-63		/* min binary exponent */
+#define	DBL_MIN_EXP	-63
+#define	FLT_MIN		1.0842021e-19	/* smallest floating number */
+#define	DBL_MIN		1.0842021e-19
+#define	FLT_MIN_10_EXP	-19
+#define	DBL_MIN_10_EXP	-19
+#define	FLT_MAX_EXP	63		/* max binary exponent */
+#define	DBL_MAX_EXP	63
+#define	FLT_MAX		9.223369e18	/* max floating number */
+#define	DBL_MAX		9.223369e18
+#define	FLT_MAX_10_EXP	18		/* max decimal exponent */
+#define	DBL_MAX_10_EXP	18
+#endif	z80
+
+#if	i8086 || m68k
+
+/*	The 8086 and 68000 use IEEE 32 and 64 bit floats */
+
+#define	FLT_MANT_DIG	24
+#define	FLT_EPSILON	1.192092896e-07
+#define	FLT_DIG		6
+#define	FLT_MIN_EXP	-125
+#define	FLT_MIN		1.175494351e-38
+#define	FLT_MIN_10_EXP	-37
+#define	FLT_MAX_EXP	128
+#define	FLT_MAX		3.402823466+38
+#define	FLT_MAX_10_EXP	38
+#define	DBL_MANT_DIG	53
+#define	DBL_EPSILON	2.220446049250313e-16
+#define	DBL_DIG		15
+#define	DBL_MIN_EXP	-1021
+#define	DBL_MIN		2.225073858507202e-308
+#define	DBL_MIN_10_EXP	-307
+#define	DBL_MAX_EXP	1024
+#define	DBL_MAX		1.797693134862315e+308
+#define	DBL_MAX_10_EXP	308
+#endif	i8086 || m68k
+
+
+/*	long double equates to double */
+
+
+#define	LDBL_MANT_DIG	DBL_MANT_DIG
+#define	LDBL_EPSILON	DBL_EPSILON
+#define	LDBL_DIG	DBL_DIG
+#define	LDBL_MIN_EXP	DBL_MIN_EXP
+#define	LDBL_MIN	DBL_MIN
+#define	LDBL_MIN_10_EXP	DBL_MIN_10_EXP
+#define	LDBL_MAX_EXP	DBL_MAX_EXP
+#define	LDBL_MAX	DBL_MAX
+#define	LDBL_MAX_10_EXP	DBL_MAX_10_EXP

compilers/HT-XA/INCLUDE/HEADERS.TAG

@@ -0,0 +1,225 @@
+_fassert	assert.h
+init_uart	conio.h
+getch	conio.h
+getche	conio.h
+putch	conio.h
+ungetch	conio.h
+kbhit	conio.h
+kbhit	conio.h
+cgets	conio.h
+cputs	conio.h
+isalpha	ctype.h
+isupper	ctype.h
+islower	ctype.h
+isdigit	ctype.h
+isxdigit	ctype.h
+isspace	ctype.h
+ispunct	ctype.h
+isalnum	ctype.h
+isprint	ctype.h
+isgraph	ctype.h
+iscntrl	ctype.h
+toupper	ctype.h
+tolower	ctype.h
+toupper	ctype.h
+tolower	ctype.h
+im	intrpt.h
+set_vector	intrpt.h
+setiva	intrpt.h
+getiva	intrpt.h
+set_vector	intrpt.h
+fabs	math.h
+floor	math.h
+ceil	math.h
+modf	math.h
+sqrt	math.h
+atof	math.h
+sin	math.h
+cos	math.h
+tan	math.h
+asin	math.h
+acos	math.h
+atan	math.h
+atan2	math.h
+frexp	math.h
+ldexp	math.h
+log	math.h
+log10	math.h
+pow	math.h
+exp	math.h
+sinh	math.h
+cosh	math.h
+tanh	math.h
+eval_poly	math.h
+setjmp	setjmp.h
+longjmp	setjmp.h
+__va_start	stdarg.h
+__va_start	stdarg.h
+__va_start	stdarg.h
+void	stdio.h
+cprintf	stdio.h
+_doprnt	stdio.h
+_doprnt	stdio.h
+_flsbuf	stdio.h
+_filbuf	stdio.h
+fclose	stdio.h
+fflush	stdio.h
+fgetc	stdio.h
+ungetc	stdio.h
+fputc	stdio.h
+getw	stdio.h
+putw	stdio.h
+fputs	stdio.h
+fread	stdio.h
+fwrite	stdio.h
+fseek	stdio.h
+rewind	stdio.h
+setbuf	stdio.h
+setvbuf	stdio.h
+fprintf	stdio.h
+fscanf	stdio.h
+vfprintf	stdio.h
+vfscanf	stdio.h
+remove	stdio.h
+rename	stdio.h
+fopen	stdio.h
+freopen	stdio.h
+fdopen	stdio.h
+ftell	stdio.h
+fgets	stdio.h
+perror	stdio.h
+_bufallo	stdio.h
+_buffree	stdio.h
+tmpnam	stdio.h
+tmpfile	stdio.h
+popen	stdio.h
+pclose	stdio.h
+void	stdio.h
+_doscan	stdio.h
+gets	stdio.h
+puts	stdio.h
+scanf	stdio.h
+sscanf	stdio.h
+vprintf	stdio.h
+vsprintf	stdio.h
+vscanf	stdio.h
+vsscanf	stdio.h
+sprintf	stdio.h
+printf	stdio.h
+atof	stdlib.h
+strtod	stdlib.h
+atoi	stdlib.h
+xtoi	stdlib.h
+atol	stdlib.h
+rand	stdlib.h
+srand	stdlib.h
+calloc	stdlib.h
+div	stdlib.h
+udiv	stdlib.h
+ldiv	stdlib.h
+uldiv	stdlib.h
+_lrotl	stdlib.h
+_lrotr	stdlib.h
+_rotl	stdlib.h
+_rotr	stdlib.h
+malloc	stdlib.h
+free	stdlib.h
+realloc	stdlib.h
+farmemcpy	stdlib.h
+farmemset	stdlib.h
+_far_alloc	stdlib.h
+_far_sbrk	stdlib.h
+nearsbrk	stdlib.h
+malloc	stdlib.h
+free	stdlib.h
+realloc	stdlib.h
+_far_alloc	stdlib.h
+_far_sbrk	stdlib.h
+farfree	stdlib.h
+farrealloc	stdlib.h
+farmemcpy	stdlib.h
+farmemset	stdlib.h
+abort	stdlib.h
+exit	stdlib.h
+atexit	stdlib.h
+getenv	stdlib.h
+system	stdlib.h
+qsort	stdlib.h
+bsearch	stdlib.h
+abs	stdlib.h
+labs	stdlib.h
+__daa	stdlib.h
+ieee_to_fastdouble	stdlib.h
+fastdouble_to_ieee	stdlib.h
+memcpy	string.h
+memmove	string.h
+strcpy	string.h
+strncpy	string.h
+strcat	string.h
+strncat	string.h
+memcmp	string.h
+strcmp	string.h
+stricmp	string.h
+strncmp	string.h
+strnicmp	string.h
+strcoll	string.h
+memchr	string.h
+strcspn	string.h
+strpbrk	string.h
+strspn	string.h
+strstr	string.h
+stristr	string.h
+strtok	string.h
+strdup	string.h
+memset	string.h
+strerror	string.h
+strlen	string.h
+strchr	string.h
+strichr	string.h
+strrchr	string.h
+strrichr	string.h
+getfreemem	sys.h
+execl	sys.h
+execv	sys.h
+execve	sys.h
+execle	sys.h
+execvp	sys.h
+execlp	sys.h
+getpid	sys.h
+mktemp	sys.h
+sync	sys.h
+fork	sys.h
+wait	sys.h
+getuid	sys.h
+setuid	sys.h
+kill	sys.h
+alarm	sys.h
+pause	sys.h
+sleep	sys.h
+setpgrp	sys.h
+getpgrp	sys.h
+spawnl	sys.h
+spawnv	sys.h
+spawnle	sys.h
+spawnve	sys.h
+spawnlp	sys.h
+spawnvp	sys.h
+chdir	sys.h
+chdrv	sys.h
+mkdir	sys.h
+rmdir	sys.h
+getcwd	sys.h
+persist_validate	sys.h
+persist_check	sys.h
+getdrv	sys.h
+_getargs	sys.h
+sbrk	sys.h
+brk	sys.h
+_pnum	sys.h
+_fnum	sys.h
+_pnum	sys.h
+_fnum	sys.h
+load_driver	sys.h
+mktime	time.h
+strftime	time.h
+__trap	xa.h

compilers/HT-XA/INCLUDE/HITECH.H

@@ -0,0 +1,119 @@
+/*	Standard types for HI-TECH Software code
+	These types may need to be tuned for different
+	machines/compilers. Notes with each one indicate assumptions
+	that should be maintained for each type.
+ */
+
+/*
+ *	$Header: /home/clyde/nz/RCS/hitech.h,v 1.8 94/04/27 13:39:06 clyde Exp $
+ *
+ *	$Log:	hitech.h,v $
+ * Revision 1.8  94/04/27  13:39:06  clyde
+ * Make FAST explicitly signed
+ * 
+ * Revision 1.7  93/05/13  00:10:56  clyde
+ * Fix #endif's
+ * 
+ * Revision 1.6  92/06/25  16:15:43  clyde
+ * Set LITTLE_ENDIAN for appropriate machines
+ * 
+ * Revision 1.5  92/06/01  15:05:44  clyde
+ * Made setting of BIG_ENDIAN conditional
+ * 
+ * Revision 1.4  91/07/18  22:57:30  clyde
+ * Added conditional setting of LARGE_DATA
+ * 
+ * Revision 1.3  91/07/08  15:37:16  clyde
+ * Added BIG_ENDIAN
+ * 
+ * Revision 1.2  89/08/09  11:57:10  clyde
+ * Added RCS header stuff
+ * 
+ */
+
+
+/*
+	Turn ANSI on if the compiler supports function prototypes and
+	has the ANSI header files
+		<stdlib.h>
+		<string.h>
+ */
+
+#if	HI_TECH_C
+#define	ANSI	1
+#endif	/* HI_TECH_C */
+
+/*	shorthand types */
+
+#define	uchar	unsigned char
+#define	ulong	unsigned long
+#define	ushort	unsigned short
+
+/* useful, tuneable types. Change only if:
+
+	1) compiler does not support type, e.g. unsigned char.
+	2) compiler generates bad code for a particular type.
+	3) a larger type would generate faster code, e.g. byte counters
+	   on the 65816 are inefficient code-wise.
+ */
+
+#define	BOOL	unsigned char		/* boolean variable. Any integral type
+					   will do. */
+#define	FAST	signed char		/* fast, small counter. Must permit
+					   values -128 to 127 but may be larger. */
+#define	UFAST	unsigned char		/* fast, small unsigned counter. Must
+					   permit values 0-255 at least */
+#define	BYTE	unsigned char		/* sizeof(BYTE) must == 1 */
+#define	INT_16	short			/* signed, >= 16 bits */
+#define	UINT_16	unsigned short		/* unsigned, >= 16 bits */
+#define	INT_32	long			/* signed, >= 32 bits */
+#define	UINT_32	unsigned long		/* unsigned, >= 32 bits */
+
+
+/*	Register variable selectors; REG1 is for things that must go
+	in registers at all costs, REG2 for things that should, REG3 for
+	things that could go in registers if there are any left over.
+	Ordering of declarations will of course come into it too.
+ */
+
+#if	z80		/* only has one register variable */
+#define	REG1	register
+#define	REG2	auto
+#define	REG3	auto
+#endif	/* z80 */
+
+#if	i8086		/* only has two register variable */
+#define	REG1	register
+#define	REG2	register
+#define	REG3	auto
+#endif	/* i8086 */
+
+#if	i8096 || m68k	/* lots of registers! */
+#define	REG1	register
+#define	REG2	register
+#define	REG3	register
+#endif	/* i8096 || m68k */
+
+/*
+ *	Little endian vs big endian
+ *	Not complete by any means.
+ */
+
+#if     !defined(BIG_ENDIAN) && !defined(LITTLE_ENDIAN)
+#if interdata || sparc || sun || m68k || m68000
+#define	BIG_ENDIAN	1
+#endif
+
+#if vax || i8086 || i386 || iAPX286
+#undef	BIG_ENDIAN
+#define	LITTLE_ENDIAN	1
+#endif
+#endif
+
+/*
+ *	Try and identify processors with large data spaces
+ */
+
+#if	sparc || m68k || m68000 || i386 || i80386 || FLAT_MODEL || vax
+#define	LARGE_DATA	1
+#endif

compilers/HT-XA/INCLUDE/INTRPT.H

@@ -0,0 +1,374 @@
+/* Definitions for interrupt handling */
+
+
+
+#ifndef	__INTRPT_H
+
+#define	__INTRPT_H
+#if	defined(i8086) && !defined(FLAT_MODEL)
+typedef far interrupt void (*isr)(void);
+#else
+typedef interrupt void (*isr)(void);
+#endif
+
+#define	_imkstr_(x)	#x
+
+/*
+ *	ROM_VECTOR, RAM_VECTOR & CHANGE_VECTOR macros for 6805, 6809,
+ *	68HC11/6801/6301 and 680x0
+ *
+ *	ROM_VECTOR: points a ROM based vector directly at an interrupt
+ *		    function.
+ *
+ *	RAM_VECTOR: points a ROM based vector at a JMP instruction in
+ *		    the "data" psect which jumps to the interrupt function.
+ *		    If "data" is linked into RAM, this results in a "soft"
+ *		    vector which can be modified.
+ *
+ *	CHANGE_VECTOR:  changes the a JMP instruction defined by RAM_VECTOR to
+ *			point at a different interrupt function.
+ *
+ *	READ_RAM_VECTOR:	returns the address of the interrupt function
+ *				to which a RAM vector effectively points.
+ *
+ *	Colin Weaver, August 1992
+ */
+
+/*
+ *	68HC11,6801,6301,6805	ei() and di()
+ */
+
+#if	m6800 || m6805
+#define	ei()	asm("	cli")
+#define	di()	asm("	sei")
+#endif	/* m6800 */
+
+/*
+ *	6805	ROM_VECTOR, RAM_VECTOR, CHANGE_VECTOR, READ_RAM_VECTOR
+ */
+
+#if	m6805
+#define ROM_VECTOR(vec, fun) \
+		asm("	ifge	(" _imkstr_(vec) "!.$F)-$E"); \
+		asm("	fail	Can't modify reset vector"); \
+		asm("	endc"); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) "!.$F"); \
+		asm("	fdb	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+#define	INIT_BYTE(addr, value) \
+		asm("	psect	absdata,abs,ovrld"); \
+		asm("	org	" _imkstr_(addr)); \
+		asm("	fcb	" _imkstr_(value)); \
+		asm("	psect	text")
+
+struct _RAM_VEC {
+	unsigned char	jmp;		/* jmp opcode */
+	interrupt void	(*addr)(void);	/* address field */
+};
+
+#define	RAM_VECTOR(vec, fun) \
+		asm("	ifge	(" _imkstr_(vec) "!.$F)-$E"); \
+		asm("	fail	Can't modify reset vector"); \
+		asm("	endc"); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) "!.$F"); \
+		asm("	fdb	999f"); \
+		asm("	psect	data,class=CODE"); \
+		asm("999:"); \
+		asm("	jmp	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+extern unsigned char	_Lvectors[];
+#define CHANGE_VECTOR(vec, fun)	(*(struct _RAM_VEC **)(_Lvectors+((vec)&0x0F)))->addr = fun
+#define	READ_RAM_VECTOR(vec)	((*(struct _RAM_VEC **)(_Lvectors+((vec)&0x0F)))->addr)
+#endif
+
+/*
+ *	68HC11, 6801, 6301, 6809 ROM_VECTOR, RAM_VECTOR, CHANGE_VECTOR, etc.
+ */
+
+#if	m6800 || m6809
+#define ROM_VECTOR(vec, fun) \
+		asm("	ifge	(" _imkstr_(vec) "!.$3F)-$3E"); \
+		asm("	fail	Can't modify reset vector"); \
+		asm("	endc"); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) "!.$3F"); \
+		asm("	fdb	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+struct _RAM_VEC {
+	unsigned char	jmp;		/* jmp opcode */
+	interrupt void	(*addr)(void);	/* address field */
+};
+
+#define	RAM_VECTOR(vec, fun) \
+		asm("	ifge	(" _imkstr_(vec) "!.$3F)-$3E"); \
+		asm("	fail	Can't modify reset vector"); \
+		asm("	endc"); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) "!.$3F"); \
+		asm("	fdb	999f"); \
+		asm("	psect	data,class=DATA"); \
+		asm("999:"); \
+		asm("	jmp	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+extern unsigned char	_Lvectors[];
+#define CHANGE_VECTOR(vec, fun)	(*(struct _RAM_VEC **)(_Lvectors+((vec)&0x3F)))->addr = fun
+#define	READ_RAM_VECTOR(vec)	((*(struct _RAM_VEC **)(_Lvectors+((vec)&0x3F)))->addr)
+#endif
+
+#if	m6809
+/* ei() and di() are for the IRQ, efi() and edi() are for FIRQ */
+
+#define	ei()	asm("	andcc	#$EF")
+#define	di()	asm("	orcc	#$10")
+#define	efi()	asm("	andcc	#$BF")
+#define	dfi()	asm("	orcc	#$40")
+#endif	/* m6809 */
+
+/*
+ *	68000 interrupt vector and interrupt handling
+ */
+
+#if	m68k
+
+#define	di()	asm("or.w #$700,sr")
+#define	ei()	asm("and.w #$F8FF,sr")
+
+#define	ROM_VECTOR(vec, fun) \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dc.l	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+struct _RAM_VEC {
+	unsigned short	jmp;		/* jmp opcode */
+	interrupt void	(*addr)(void);	/* address field */
+};
+
+#define	RAM_VECTOR(vec, fun) \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dc.l	999f"); \
+		asm("	psect	data,class=DATA"); \
+		asm("999:"); \
+		asm("	jmp	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+extern unsigned char	_Lvectors[];
+#define CHANGE_VECTOR(vec, fun)	(*(struct _RAM_VEC **)(_Lvectors+(vec)))->addr = fun
+#define	READ_RAM_VECTOR(vec)	((*(struct _RAM_VEC **)(_Lvectors+(vec)))->addr)
+
+#endif	/* m68k */
+
+#if	i8051
+
+/*
+ *	8051 interrupt vector and interrupt handling
+ */
+
+#define	ei()	asm("	setb	ea")
+#define	di()	asm("	clr	ea")
+
+#define	ROM_VECTOR(vec, fun) \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	ljmp	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+#define	RAM_VECTOR(vec, fun) \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	psect	vectors,ovrld"); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	push	999f+1"); \
+		asm("	push	999f"); \
+		asm("	ret"); \
+		asm("	psect	rdata,class=DATA"); \
+		asm("999:"); \
+		asm("	dw	_" _imkstr_(fun)); \
+		asm("	psect	text");
+
+extern near isr * code  _Lvectors[];
+
+#define	CHANGE_VECTOR(vec, fun)	(*_Lvectors[(vec)+3] = fun)
+#define	READ_RAM_VECTOR(vec)	(*_Lvectors[(vec)+3])
+
+#endif	/* i8051 */
+
+#ifdef	ROM_VECTOR
+#define	set_vector(vec, fun)	ROM_VECTOR(vec, fun)
+#endif
+
+#if	i8096
+#define	ei()	asm("	ei")
+#define	di()	asm("	di")
+#define	set_vector(vec, fun) \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) " and 0x7F"); \
+		asm("	dcw	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+#endif	/* i8096 */
+
+#if	h8300
+#define	ei()	asm("	andc	#H'7F,ccr")
+#define	di()	asm("	orc	#H'80,ccr")
+#define	set_vector(vec, fun) \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) " and H'FF"); \
+		asm("	dc.w	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+#endif	/* h8300 */
+
+#if	h8300h
+#define	ei()	asm("	andc	#H'7F,ccr")
+#define	di()	asm("	orc	#H'80,ccr")
+#define	set_vector(vec, fun) \
+		asm("	psect	vectors,ovrld"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec) " and H'FF"); \
+		asm("	dc.l	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+#endif	/* h8300 */
+#if	i8086
+#define	ei()	asm("	sti")
+#define	di()	asm("	cli")
+#endif	/* i8086 */
+
+#if	z80
+#define	ei()	asm("	ei")
+#define	di()	asm("	di")
+extern void	im(unsigned char);
+
+
+/*
+ *	Z80 interrupt mode 2 vector command
+ */
+
+#define ROM_VECTOR(vec, fun) \
+		asm("	psect	im2vecs,class=CODE,ovrld,reloc=256"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	defw	_" _imkstr_(fun)); \
+		asm("	psect	text")
+
+struct _RAM_VEC {
+        unsigned char   jmp;            /* jmp opcode */
+        unsigned int    addr;           /* address field */
+};
+
+#define RAM_VECTOR(vec, fun) \
+                asm("   psect   im2vecs,class=CODE,ovrld,size=256,reloc=256"); \
+                asm("   org     " _imkstr_(vec)); \
+                asm("   defw    999f"); \
+                asm("   psect   data,class=DATA"); \
+                asm("999:"); \
+                asm("   jp      _" _imkstr_(fun)); \
+                asm("   psect   text")
+
+extern unsigned char    _Lim2vecs[];
+#define CHANGE_VECTOR(vec, fun) (*(struct _RAM_VEC **)(_Lim2vecs+((vec)&0xFF)))->addr = ((unsigned)(fun))
+#define READ_RAM_VECTOR(vec)    ((void interrupt (*)(void))((*(struct _RAM_VEC **)(_Lim2vecs+((vec)&0xFF)))->addr))
+#endif	z80
+
+#if	_XA_
+
+#define	_iexpand_(a)	a
+#define	ei()	asm("	setb	337h")
+#define	di()	asm("	clr	337h")
+
+struct _RAM_VEC {
+	unsigned short	jmp;		/* jmp opcode */
+	interrupt void	(*addr)(void);	/* address field */
+};
+
+#if	LARGE_MODEL | HUGE_MODEL
+#define	ROM_VECTOR(vec, fun, psw) \
+		asm("	psect	vectors,ovrld,align=2,class=CODE,space=0"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dw	"_imkstr_(psw)", 999f"); \
+		asm("	psect	text"); \
+		asm("999:	fjmp	_" _imkstr_(fun));
+
+#define	RAM_VECTOR(vec, fun, psw) \
+		asm("	psect	vectors,ovrld,align=2,class=CODE,space=0"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dw	"_imkstr_(psw)", 999f"); \
+		asm("	psect	text"); \
+		asm("999:	push.w	__Vc" _imkstr_(vec) "__"); \
+		asm("	push.w	__Vc" _imkstr_(vec) "__+2"); \
+		asm("	ret"); \
+		asm("	psect	rdata,size=1024,class=DATA,space=0"); \
+		asm("	global	__Vc" _imkstr_(vec) "__"); \
+		asm("__Vc" _imkstr_(vec) "__:"); \
+		asm("	dw	_" _imkstr_(fun) " and 0ffffh"); \
+		asm("	dw	_" _imkstr_(fun) " shr 16"); \
+		extern isr _Vc ## _iexpand_(vec) ## __
+
+#else	/* LARGE_MODEL */
+
+#define	ROM_VECTOR(vec, fun, psw) \
+		asm("	psect	vectors,ovrld,align=2,class=CODE,space=0"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dw	"_imkstr_(psw)", _" _imkstr_(fun));
+
+#define	RAM_VECTOR(vec, fun, psw) \
+		asm("	psect	vectors,ovrld,align=2,class=CODE,space=0"); \
+		asm("	global	_" _imkstr_(fun)); \
+		asm("	org	" _imkstr_(vec)); \
+		asm("	dw	"_imkstr_(psw)", 999f"); \
+		asm("	psect	text"); \
+		asm("999:	push.w	__Vc" _imkstr_(vec) "__"); \
+		asm("	ret"); \
+		asm("	psect	rdata,size=1024,class=DATA,space=0"); \
+		asm("	global	__Vc" _imkstr_(vec) "__"); \
+		asm("__Vc" _imkstr_(vec) "__:"); \
+		asm("	dw	_" _imkstr_(fun)); \
+		extern isr _Vc ## _iexpand_(vec) ## __
+#endif
+
+
+#define	USE_RAM_VECTOR(vec)	extern isr _Vc ## _iexpand_(vec) ## __
+#define CHANGE_VECTOR(vec, fun) (_Vc ## _iexpand_(vec) ## __ = (fun))
+#define	READ_RAM_VECTOR(vec)	(_Vc ## _iexpand_(vec) ## __)
+
+#endif	/* _XA_ */
+
+/*	The type of a pointer to an interrupt vector */
+
+#if	defined(i8086) && !defined(FLAT_MODEL)
+
+extern isr set_vector(volatile far isr *, isr);
+
+#if	_HOSTED
+extern isr setiva(int, isr);
+extern isr getiva(int);
+#endif	/* _HOSTED */
+
+#else	/* i8086 */
+
+#ifndef	set_vector
+extern isr set_vector(volatile isr *, isr);
+#endif
+
+#endif	/* i8086 */
+
+#endif	/* __INTRPT_H */

compilers/HT-XA/INCLUDE/LIMITS.H

@@ -0,0 +1,26 @@
+/*	Characteristics of integral types */
+
+#define	CHAR_BIT	8		/* bits per char */
+#define	CHAR_MAX	127		/* max value of a char */
+#define	CHAR_MIN	-128		/* min value */
+#define	SCHAR_MAX	CHAR_MAX	/* chars are signed */
+#define	SCHAR_MIN	CHAR_MIN
+#define	UCHAR_MAX	255		/* for unsigned chars */
+#define	SHRT_MAX	32767		/* max value of a short */
+#define	SHRT_MIN	(int)-32768
+#define	USHRT_MAX	65535		/* unsigned short */
+
+/*	32 bit chips have 32 bit integers */
+
+#if	defined(m68k) || defined(i8086) && defined(FLAT_MODEL)
+#define	INT_MAX		2147483647	/* max value of int */
+#define	INT_MIN		(int)-2147483648	/* min value */
+#define	UINT_MAX	4294967295	/* unsigned int */
+#else	/* not 32 bit chips */
+#define	INT_MAX		32767		/* max for int */
+#define	INT_MIN		(int)-32768	/* min for int */
+#define	UINT_MAX	65535		/* unsigned int */
+#endif	/* 32 bit chips */
+#define	LONG_MAX	2147483647	/* max value of long */
+#define	LONG_MIN	(long)-2147483648	/* min value */
+#define	ULONG_MAX	4294967295	/* unsigned long */

compilers/HT-XA/INCLUDE/MATH.H

@@ -0,0 +1,23 @@
+extern double fabs(double);
+extern double floor(double);
+extern double ceil(double);
+extern double modf(double, double *);
+extern double sqrt(double);
+extern double atof(const char *);
+extern double sin(double);
+extern double cos(double);
+extern double tan(double);
+extern double asin(double);
+extern double acos(double);
+extern double atan(double);
+extern double atan2(double, double);
+extern double frexp(double, int *);
+extern double ldexp(double, int);
+extern double log(double);
+extern double log10(double);
+extern double pow(double, double);
+extern double exp(double);
+extern double sinh(double);
+extern double cosh(double);
+extern double tanh(double);
+extern double eval_poly(double, const double *, int);

compilers/HT-XA/INCLUDE/SETJMP.H

@@ -0,0 +1,41 @@
+#ifndef	__SETJMP_H
+#define	__SETJMP_H
+
+#if	defined(z80)
+typedef	int	jmp_buf[5];
+
+#elif	defined(i8086)
+typedef	int	jmp_buf[8];
+
+#elif	defined(i8096)
+typedef	int	jmp_buf[10];
+
+#elif	defined(m68k)
+typedef	int	jmp_buf[10];
+
+#elif	defined(_XA_)
+typedef	int	jmp_buf[6];
+
+#elif	defined(m6809)
+typedef	int	jmp_buf[4];
+
+#elif	defined(m6800)
+typedef	int	jmp_buf[2];
+
+#elif	defined(i8051)
+typedef int	jmp_buf[4];
+
+#elif	defined(h8300)||defined(h8300h)
+typedef int	jmp_buf[2];
+
+#elif	defined(m6805)
+#error	setjmp() and longjmp() cannot be implemented on the 6805
+
+#else
+#error	setjmp.h: Processor type not supported, or not defined.
+#endif
+
+extern	int	setjmp(jmp_buf);
+extern void	longjmp(jmp_buf, int);
+
+#endif	/* __SETJMP_H */

compilers/HT-XA/INCLUDE/STDARG.H

@@ -0,0 +1,57 @@
+/*	Macros for accessing variable arguments */
+
+#ifndef	_STDARG
+
+#if	(defined(i8051) && !defined(EXTERNAL_STACK))
+typedef near void * va_list[1];
+#define	va_start(ap, parmn)	*ap = __va_start((void *)&parmn)
+#pragma inline(__va_start)
+extern near void *		__va_start(void *);
+#define	va_arg(ap, type)	(*--*(type near **)(ap))
+#define	_STDARG
+#elif	defined(m6805)
+typedef near void * va_list[1];
+#define	va_start(ap, parmn)	*ap = __va_start()
+#pragma inline(__va_start)
+extern near void *		__va_start(void);
+#define	va_arg(ap, type)	(*(*(type near **)ap)++)
+#define	_STDARG
+#elif	defined(_MPC_)
+typedef void * va_list[1];
+#define	va_start(ap, parmn)	*ap = __va_start()
+#pragma inline(__va_start)
+extern void *		__va_start(void);
+#define	va_arg(ap, type)	(*(*(type **)ap)++)
+#define	_STDARG
+#else
+typedef void *	va_list[1];
+#endif
+
+#ifdef	i8086
+#ifdef	FLAT_MODEL
+#define	_STACK_ALIGN	4
+#else
+#define	_STACK_ALIGN	2
+#endif
+#endif
+
+#if	defined(z80) || defined(_XA_)
+#define	_STACK_ALIGN	2
+#endif
+
+#ifdef	_STACK_ALIGN	
+#define	va_start(ap, parmn)	*ap = (char *)&parmn + ((sizeof(parmn)+_STACK_ALIGN-1)&~(_STACK_ALIGN-1))
+#define	va_arg(ap, type)	(*(*(type **)ap)++)
+#define	_STDARG
+#endif
+
+#ifndef	_STDARG
+#define	va_start(ap, parmn)	*ap = (char *)&parmn + sizeof parmn
+#define	va_arg(ap, type)	(*(*(type **)ap)++)
+#define	_STDARG
+#endif
+
+#define	va_end(ap)
+
+
+#endif	/* STDARG */

compilers/HT-XA/INCLUDE/STDDEF.H

@@ -0,0 +1,13 @@
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+#endif	_STDDEF
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	NULL
+
+extern int	errno;			/* system error number */

compilers/HT-XA/INCLUDE/STDIO.H

@@ -0,0 +1,195 @@
+#ifndef	_STDIO_H_
+#define	_STDIO_H_
+#if	z80
+#define	BUFSIZ		512
+#define	_NFILE		8
+#else	/* z80 */
+#define	BUFSIZ		1024
+#define	_NFILE		20
+#endif	/* z80 */
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+#endif	/* _STDDEF */
+
+#ifndef	_STDARG
+#include	<stdarg.h>
+#endif
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	/* NULL */
+
+extern int	errno;			/* system error number */
+
+#ifndef FILE
+#define	uchar	unsigned char
+
+#if	_HOSTED
+extern	struct	_iobuf {
+	char *		_ptr;
+	int		_cnt;
+	char *		_base;
+	unsigned short	_flag;
+	short		_file;
+	size_t		_size;
+} _iob[_NFILE];
+
+#define	FILE		struct _iobuf
+
+#define	L_tmpnam	81		/* max length of temporary names */
+#define	_MAXTFILE	8		/* max number of temporary files */
+
+#if	DOS
+#define	FILENAME_MAX	81		/* max length of a pathname */
+#define	FOPEN_MAX	5
+#endif
+
+extern struct _tfiles {
+	char	tname[L_tmpnam];
+	FILE *	tfp;
+}	* _tfilesptr;
+
+#else	/* _HOSTED */
+
+struct __prbuf
+{
+	char *		ptr;
+	void (*		func)(char);
+};
+#endif	/* _HOSTED */
+#endif	/* FILE */
+
+#define	_IOFBF		0
+#define	_IOREAD		01
+#define	_IOWRT		02
+#define	_IORW		03
+#define	_IONBF		04
+#define	_IOMYBUF	010
+#define	_IOEOF		020
+#define	_IOERR		040
+#define	_IOSTRG		0100
+#define	_IOBINARY	0200
+#define	_IOLBF		0400
+#define	_IODIRN		01000	/* true when file is in write mode */
+#define	_IOAPPEND	02000	/* file was opened in append mode */
+#define	_IOSEEKED	04000	/* a seek has occured since last write */
+#define	_IOTMPFILE	010000	/* this file is a temporary */
+
+#define	EOF		(-1)
+#define	_IOSTRING	(-67)
+
+#define	SEEK_SET	0
+#define	SEEK_CUR	1
+#define	SEEK_END	2
+#define	TMP_MAX		255
+
+#if	_HOSTED
+#define	stdin		(&_iob[0])
+#define	stdout		(&_iob[1])
+#define	stderr		(&_iob[2])
+#ifdef	DOS
+#define	stdprn		(&_iob[3])
+#endif
+#define	getchar()	getc(stdin)
+#define	putchar(x)	putc(x,stdout)
+#else	/* _HOSTED */
+#include	<conio.h>
+#define	getchar()	getche()
+#define	putchar(x)	putch(x)
+extern int	cprintf(char *, ...);
+#pragma printf_check(cprintf)
+#ifdef	_MPC_
+extern void	_doprnt(char *, const register char *, ...);
+#else
+extern int	_doprnt(struct __prbuf *, const register char *, register va_list);
+#endif	/* _MPC_ */
+#endif	/* _HOSTED */
+
+/*	getc() and putc() must be functions for CP/M to allow the special
+ *	handling of '\r', '\n' and '\032'. The same for MSDOS except that
+ *	it at least knows the length of a file.
+ */
+
+#define	getc(p)		fgetc(p)
+#define	putc(x,p)	fputc(x,p)
+
+#define	feof(p)		(((p)->_flag&_IOEOF)!=0)
+#define	ferror(p)	(((p)->_flag&_IOERR)!=0)
+#define	fileno(p)	((unsigned short)p->_file)
+#define	clrerr(p)	p->_flag &= ~_IOERR
+#define	clreof(p)	p->_flag &= ~_IOEOF
+#define	clearerr(p)	p->_flag &= ~(_IOERR|_IOEOF)
+
+
+#if	_HOSTED
+extern int	_flsbuf(char, FILE *);
+extern int	_filbuf(FILE *);
+extern int	fclose(FILE *);
+extern int	fflush(FILE *);
+extern int	fgetc(FILE *);
+extern int	ungetc(int, FILE *);
+extern int	fputc(int, FILE *);
+extern int	getw(FILE *);
+extern int	putw(int, FILE *);
+extern int	fputs(const char *, FILE *);
+extern int	fread(void *, size_t, size_t, FILE *);
+extern int	fwrite(const void *, size_t, size_t, FILE *);
+extern int	fseek(FILE *, long, int);
+extern int	rewind(FILE *);
+extern void	setbuf(FILE *, char *);
+extern int	setvbuf(FILE *, char *, int, size_t);
+extern int	fprintf(FILE *, const char *, ...);
+extern int	fscanf(FILE *, const char *, ...);
+extern int	vfprintf(FILE *, const char *, va_list);
+extern int	vfscanf(FILE *, const char *, va_list);
+extern int	remove(const char *);
+extern int	rename(const char *, const char *);
+extern FILE *	fopen(const char *, const char *);
+extern FILE *	freopen(const char *, const char *, FILE *);
+extern FILE *	fdopen(int, const char *);
+extern long	ftell(FILE *);
+extern char *	fgets(char *, int, FILE *);
+extern void	perror(const char *);
+extern char *	_bufallo(void);
+extern void	_buffree(char *);
+extern char *	tmpnam(char *);
+extern FILE *	tmpfile(void);
+
+#if	unix
+extern FILE *	popen(char *, char *);
+extern int	pclose(FILE *);
+#endif
+extern void	(*_atexitptr)(void);
+
+#pragma	printf_check(fprintf)
+
+#endif	/* __HOSTED */
+
+#ifdef	_MPC_
+extern int	_doscan(const char *, const char *, va_list);
+#define vprintf(s, l)		_doprnt(0, (s), (l))
+#define vsprintf(b, s, l)	_doprnt((b), (s), (l))
+#define	vscanf(s, l)		_doscan(0, (s), (l))
+#define	vsscanf(b, s, l)		_doscan((b), (s), (l))
+#else
+extern char *	gets(char *);
+extern int	puts(const char *);
+extern int	scanf(const char *, ...);
+extern int	sscanf(const char *, const char *, ...);
+extern int	vprintf(const char *, va_list);
+extern int	vsprintf(char *, const char *, va_list);
+extern int	vscanf(const char *, va_list ap);
+extern int	vsscanf(const char *, const char *, va_list);
+
+#endif	/* _MPC_ */
+
+#pragma	printf_check(printf)
+#pragma	printf_check(sprintf)
+extern int	sprintf(char *, const char *, ...);
+extern int	printf(const char *, ...);
+#endif	/* _STDIO_H_ */

compilers/HT-XA/INCLUDE/STDLIB.H

@@ -0,0 +1,145 @@
+/*	Standard utility functions */
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef unsigned short	wchar_t;	/* wide char type */
+
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+
+#define	_STDDEF
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	NULL
+
+extern int	errno;			/* system error number */
+#endif	_STDDEF
+
+#ifndef	_STDLIB_
+#define	_STDLIB_
+#define	RAND_MAX	32767		/* max value returned by rand() */
+#define	EXIT_SUCCESS	0
+#define	EXIT_FAILURE	1
+
+#ifndef	_DIVTYPES
+#ifdef	_MPC_
+typedef struct {
+	int	rem;	/* remainder */		/* PIC version returns remainder here */
+	int	__div_dummy;
+	int	quot;	/* quotient */
+} div_t;				/* div() return type */
+typedef struct {
+	unsigned	rem;	/* remainder */		/* PIC version returns remainder here */
+	unsigned	__div_dummy;
+	unsigned	quot;	/* quotient */
+} udiv_t;				/* div() return type */
+typedef struct {
+	long 	rem;	/* remainder */
+	long	_dummy;
+	long 	quot;	/* quotient */
+} ldiv_t;				/* ldiv() return type */
+typedef struct {
+	unsigned long 	rem;	/* remainder */
+	unsigned long	_dummy;
+	unsigned long 	quot;	/* quotient */
+} uldiv_t;				/* ldiv() return type */
+#else
+typedef struct {
+	int	quot;	/* quotient */
+	int	rem;	/* remainder */
+} div_t;				/* div() return type */
+typedef struct {
+	unsigned	quot;	/* quotient */
+	unsigned	rem;	/* remainder */
+} udiv_t;				/* div() return type */
+typedef struct {
+	long 	quot;	/* quotient */
+	long 	rem;	/* remainder */
+} ldiv_t;				/* ldiv() return type */
+typedef struct {
+	unsigned long 	quot;	/* quotient */
+	unsigned long 	rem;	/* remainder */
+} uldiv_t;				/* ldiv() return type */
+#endif	_MPC_
+
+#define	_DIVTYPES
+#endif
+
+extern double		atof(const char *);
+extern double		strtod(const char *, const char **);
+extern int		atoi(const char *);
+extern unsigned		xtoi(const char *);
+extern long		atol(const char *);
+extern int		rand(void);
+extern void		srand(unsigned int);
+extern void *		calloc(size_t, size_t);
+extern div_t		div(int numer, int denom);
+extern udiv_t		udiv(unsigned numer, unsigned denom);
+extern ldiv_t		ldiv(long numer, long denom);
+extern uldiv_t		uldiv(unsigned long numer,unsigned  long denom);
+extern unsigned long	_lrotl(unsigned long value, unsigned int shift);
+extern unsigned long	_lrotr(unsigned long value, unsigned int shift);
+extern unsigned int	_rotl(unsigned int value, unsigned int shift);
+extern unsigned int	_rotr(unsigned int value, unsigned int shift);
+
+#define	max(a,b)	(((a) > (b)) ? (a) : (b))
+#define	min(a,b)	(((a) < (b)) ? (a) : (b))
+
+#if	i8086 && !FLAT_MODEL
+enum {	_NO_EMS = 0, _USE_EMS };
+#endif
+
+#if	i8086 && LARGE_DATA
+extern void *	malloc(size_t);
+extern void	free(far void *);
+extern void *	realloc(far void *, size_t);
+extern void *	farmemcpy(far void *, far void *, size_t);
+extern void *	farmemset(far void *, int, size_t);
+extern void *	_far_alloc(size_t, char);
+extern void *	_far_sbrk(size_t, char);
+extern near void *	nearsbrk(size_t);
+#define	farmalloc(n)	_far_alloc(n, _USE_EMS)
+#define	farfree(p)	free(p)
+#define	farrealloc(p,n)	realloc(p,n)
+#define	_non_ems_alloc(x)	_far_alloc(x, _NO_EMS)
+#define	_non_ems_sbrk(x)	_far_sbrk(x, _NO_EMS)
+#else
+extern void *		malloc(size_t);
+extern void		free(void *);
+extern void *		realloc(void *, size_t);
+#define	_non_ems_alloc(x)	malloc(x)
+#define	_non_ems_sbrk(x)	sbrk(x)
+#if	i8086 && !FLAT_MODEL
+extern far void *	_far_alloc(size_t, char);
+extern far void *	_far_sbrk(size_t, char);
+#define	farmalloc(n)	_far_alloc(n, _USE_EMS)
+extern void		farfree(far void *);
+extern far void *	farrealloc(far void *, size_t);
+extern far void *	farmemcpy(far void *, far void *, size_t);
+extern far void *	farmemset(far void *, int, size_t);
+#endif	/* i8086 */
+#endif	/* i8086 && LARGE_DATA */
+
+extern void	abort(void);
+extern void	exit(int);
+extern int	atexit(void (*)(void));
+extern char *	getenv(const char *);
+extern char **	environ;
+extern int	system(char *);
+extern void	qsort(void *, size_t, size_t, int (*)(const void *, const void *));
+extern void *	bsearch(const void *, void *, size_t, size_t, int(*)(const void *, const void *));
+extern int	abs(int);
+extern long	labs(long);
+#endif
+
+
+#ifdef	z80
+extern unsigned char __daa(unsigned char);
+#pragma	inline(__daa)
+#endif
+
+#if	defined(_XA_) && sizeof(double) == 8
+extern double	ieee_to_fastdouble(double);
+extern double	fastdouble_to_ieee(double);
+#endif

compilers/HT-XA/INCLUDE/STRING.H

@@ -0,0 +1,57 @@
+/*	String functions */
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+extern int	errno;			/* system error number */
+
+#endif	_STDDEF
+
+#if	defined(_PIC14) || defined(_PIC12)
+#define	__CONST	const
+#else
+#define	__CONST
+#endif
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	NULL
+
+extern void *	memcpy(void *, const void *, size_t);
+extern void *	memmove(void *, const void *, size_t);
+extern char *	strcpy(char *, const char *);
+extern char *	strncpy(char *, const char *, size_t);
+extern char *	strcat(char *, const char *);
+extern char *	strncat(char *, const char *, size_t);
+extern int	memcmp(const void *, const void *, size_t);
+extern int	strcmp(const char *, const char *);
+extern int	stricmp(const char *, const char *);
+extern int	strncmp(const char *, const char *, size_t);
+extern int	strnicmp(const char *, const char *, size_t);
+extern size_t	strcoll(char *, size_t, char *);
+extern __CONST void *	memchr(const void *, int, size_t);
+extern size_t	strcspn(const char *, const char *);
+extern __CONST char *	strpbrk(const char *, const char *);
+extern size_t	strspn(const char *, const char *);
+extern __CONST char *	strstr(const char *, const char *);
+extern __CONST char *	stristr(const char *, const char *);
+extern char *	strtok(char *, const char *);
+extern char *	strdup(const char *);
+extern void *	memset(void *, int, size_t);
+extern char *	strerror(int);
+extern size_t	strlen(const char *);
+extern __CONST char *	strchr(const char *, int);
+extern __CONST char *	strichr(const char *, int);
+extern __CONST char *	strrchr(const char *, int);
+extern __CONST char *	strrichr(const char *, int);
+
+#ifdef	z80
+#pragma	inline(memcpy)
+#pragma	inline(memset)
+#pragma	inline(strcpy)
+#pragma	inline(strlen)
+#pragma	inline(strcmp)
+#endif

compilers/HT-XA/INCLUDE/SYS.H

@@ -0,0 +1,95 @@
+/*
+ *	System-dependent functions.
+ */
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef	unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+#endif	_STDDEF
+
+#ifndef	NULL
+#define	NULL	((void *)0)
+#endif	NULL
+
+extern int	errno;			/* system error number */
+
+#if	defined(DOS)
+#ifndef	_FREEMEM
+#define	_FREEMEM
+struct freemem {
+	unsigned long 	fr_dosmem;
+	unsigned long	fr_extmem;
+};
+#endif
+extern void	getfreemem(struct freemem *);
+#endif
+
+extern int	execl(char *, char *, ...);
+extern int	execv(char *, char **);
+extern int	execve(char *, char **, char **);
+extern int	execle(char *, char *, ...);
+extern int	execvp(char *, char **);
+extern int	execlp(char *, char *, ...);
+extern int	getpid(void);
+extern char *	mktemp(char *);
+#if	defined(unix) || defined(ATDOS)
+extern void	sync(void);
+extern int	fork(void);
+extern int	wait(int *);
+extern int	getuid(void);
+extern int	setuid(int);
+extern int	kill(int, int);
+extern int	alarm(int);
+extern int	pause(void);
+extern void	sleep(unsigned int);
+extern int	setpgrp(void);
+extern int	getpgrp(void);
+#else	unix
+extern int	spawnl(char *, char *, ...);
+extern int	spawnv(char *, char **);
+extern int	spawnle(char *, char *, ...);
+extern int	spawnve(char *, char **, char **);
+extern int	spawnlp(char *, char *, ...);
+extern int	spawnvp(char *, char **);
+#endif	unix
+extern int	chdir(char *);
+extern int	chdrv(char *);
+extern int	mkdir(char *);
+extern int	rmdir(char *);
+extern char *	getcwd(char *);
+extern void	persist_validate(void);
+extern int	persist_check(int);
+extern char *	getdrv(void);
+extern char **	_getargs(char *, char *);
+extern int	_argc_;
+
+#if	z80 || i8086
+#define	inp(p)		(*(port unsigned char *)(p))
+#define	outp(p,v)	(*(port unsigned char *)(p) = (v))
+#if	i8086
+#define	inpw(p)		(*(port unsigned short *)(p))
+#define	outpw(p,v)	(*(port unsigned short *)(p) = (v))
+#endif
+#endif
+
+extern void *	sbrk(size_t);
+extern void	brk(void *);
+#if	_HOSTED
+struct _iob;
+extern int	_pnum(unsigned long, signed char, signed char, unsigned char, unsigned char, struct _iobuf *, unsigned char);
+extern int	_fnum(double, short, short, short, struct _iobuf *, short);
+#else
+extern int	_pnum(unsigned long, signed char, signed char, unsigned char, unsigned char, struct __prbuf *, unsigned char);
+extern int	_fnum(double, short, short, short, struct __prbuf *, short);
+#endif
+
+#if	defined(ATDOS)
+extern int	load_driver(char *);
+extern int	send_message(unsigned short, unsigned short, unsigned long,
+			unsigned long, void *, unsigned short);
+extern int	get_message(unsigned short *, unsigned long *, void *,
+			unsigned short *);
+#endif

compilers/HT-XA/INCLUDE/TIME.H

@@ -0,0 +1,42 @@
+#ifndef	_TIME
+
+#ifndef	_STDDEF
+typedef	int		ptrdiff_t;	/* result type of pointer difference */
+typedef	unsigned	size_t;		/* type yielded by sizeof */
+typedef unsigned short	wchar_t;	/* wide char type */
+#define	_STDDEF
+#define	offsetof(ty, mem)	((int)&(((ty *)0)->mem))
+#endif	_STDDEF
+
+typedef	long	time_t;		/* for representing times in seconds */
+struct tm {
+	int	tm_sec;
+	int	tm_min;
+	int	tm_hour;
+	int	tm_mday;
+	int	tm_mon;
+	int	tm_year;
+	int	tm_wday;
+	int	tm_yday;
+	int	tm_isdst;
+};
+
+#define	CLOCKS_PER_SEC	1
+#define	clock()	(-1L)
+#define	difftime(t1, t0)	((double)((time_t)(t1)-(time_t)(t0)))
+#define	_TIME
+#endif	_TIME
+
+extern int	time_zone;	/* minutes WESTWARD of Greenwich */
+				/* this value defaults to 0 since with
+				   operating systems like MS-DOS there is
+				   no time zone information available */
+
+extern time_t	time(time_t *);	/* seconds since 00:00:00 Jan 1 1970 */
+extern int	stime(time_t *);	/* set time */
+extern char *	asctime(struct tm *);	/* converts struct tm to ascii time */
+extern char *	ctime(time_t *);	/* current local time in ascii form */
+extern struct tm *	gmtime(time_t *);	/* Universal time */
+extern struct tm *	localtime(time_t *);	/* local time */
+extern time_t		mktime(struct tm *);
+extern size_t		strftime(char *, size_t, const char *, const struct tm *);

compilers/HT-XA/INCLUDE/XA.H

@@ -0,0 +1,247 @@
+/*
+ *	XA G3 SFR definitions
+ *	Extracted directly from Philips documentation
+ */
+
+#ifndef	__xa_h__
+#define	__xa_h__
+
+extern unsigned int	__trap(unsigned char, ...);
+#pragma inline(__trap)
+
+static unsigned short	PSW	@ 0x400;	/* Program status word */
+static unsigned char	PSWL	@ 0x400;	/* Program status word (low byte) */
+static unsigned char	PSWH	@ 0x401;	/* Program status word (high byte) */
+static unsigned char	PSW51	@ 0x402;	/* 80C51 compatible PSW */
+static unsigned char	SSEL	@ 0x403;	/* Segment selection register */
+static unsigned char	PCON	@ 0x404;	/* Power control register */
+static unsigned char	TCON	@ 0x410;	/* Timer 0 and 1 control register */
+static unsigned char	TSTAT	@ 0x411;	/* Timer 0 and 1 extended status */
+static unsigned char	T2CON	@ 0x418;	/* Timer 2 control register */
+static unsigned char	T2MOD	@ 0x419;	/* Timer 2 mode control */
+static unsigned char	WDCON	@ 0x41F;	/* Watchdog control register */
+static unsigned char	S0CON	@ 0x420;	/* Serial port 0 control register */
+static unsigned char	S0STAT	@ 0x421;	/* Serial port 0 extended status */
+static unsigned char	S1CON	@ 0x424;	/* Serial port 1 control register */
+static unsigned char	S1STAT	@ 0x425;	/* Serial port 1 extended status */
+static unsigned char	IEL	@ 0x426;	/* Interrupt enable low byte */
+static unsigned char	IEH	@ 0x427;	/* Interrupt enable high byte */
+static unsigned char	SWR	@ 0x42A;	/* Software Interrupt Request */
+static unsigned char	P0	@ 0x430;	/* Port 0 */
+static unsigned char	P1	@ 0x431;	/* Port 1 */
+static unsigned char	P2	@ 0x432;	/* Port 2 */
+static unsigned char	P3	@ 0x433;	/* Port3 */
+static unsigned char	SCR	@ 0x440;	/* System configuration register */
+static unsigned char	DS	@ 0x441;	/* Data segment */
+static unsigned char	ES	@ 0x442;	/* Extra segment */
+static unsigned char	CS	@ 0x443;	/* Code segment */
+static unsigned char	TL0	@ 0x450;	/* Timer 0 low byte */
+static unsigned char	TH0	@ 0x451;	/* Timer 0 high byte */
+static unsigned char	TL1	@ 0x452;	/* Timer 1 low byte */
+static unsigned char	TH1	@ 0x453;	/* Timer 1 high byte */
+static unsigned char	RTL0	@ 0x454;	/* Timer 0 extended reload, low byte */
+static unsigned char	RTH0	@ 0x455;	/* Timer 0 extended reload, high byte */
+static unsigned char	RTL1	@ 0x456;	/* Timer 1 extended reload, low byte */
+static unsigned char	RTH1	@ 0x457;	/* Timer 1 extended reload, high byte */
+static unsigned char	TL2	@ 0x458;	/* Timer 2 low byte */
+static unsigned char	TH2	@ 0x459;	/* Timer 2 high byte */
+static unsigned char	T2CAPL	@ 0x45A;	/* Timer 2 capture register, low byte */
+static unsigned char	T2CAPH	@ 0x45B;	/* Timer 2 capture register, high byte */
+static unsigned char	TMOD	@ 0x45C;	/* Timer 0 and 1 mode register */
+static unsigned char	WFEED1	@ 0x45D;	/* Watchdog feed 1 */
+static unsigned char	WFEED2	@ 0x45E;	/* Watchdog feed 2 */
+static unsigned char	WDL	@ 0x45F;	/* Watchdog timer reload */
+static unsigned char	S0BUF	@ 0x460;	/* Serial port 0 buffer register */
+static unsigned char	S0ADDR	@ 0x461;	/* Serial port 0 address register */
+static unsigned char	S0ADEN	@ 0x462;	/* Serial port 0 address enable register */
+static unsigned char	S1BUF	@ 0x464;	/* Serial port 1 buffer register */
+static unsigned char	S1ADDR	@ 0x465;	/* Serial port 1 address register */
+static unsigned char	S1ADEN	@ 0x466;	/* Serial port 1 address enable register */
+static unsigned char	BTRL	@ 0x468;	/* Bus timing register high byte */
+static unsigned char	BTRH	@ 0x469;	/* Bus timing register low byte */
+static unsigned char	BCR	@ 0x46A;	/* Bus configuration register */
+static unsigned char	P0CFGA	@ 0x470;	/* Port 0 configuration A */
+static unsigned char	P1CFGA	@ 0x471;	/* Port 1 configuration A */
+static unsigned char	P2CFGA	@ 0x472;	/* Port 2 configuration A */
+static unsigned char	P3CFGA	@ 0x473;	/* Port 3 configuration A */
+static unsigned char	SWE	@ 0x47A;	/* Software Interrupt Enable */
+static unsigned char	IPA0	@ 0x4A0;	/* Interrupt priority 0 */
+static unsigned char	IPA1	@ 0x4A1;	/* Interrupt priority 1 */
+static unsigned char	IPA2	@ 0x4A2;	/* Interrupt priority 2 */
+static unsigned char	IPA4	@ 0x4A4;	/* Interrupt priority 4 */
+static unsigned char	IPA5	@ 0x4A5;	/* Interrupt priority 5 */
+static unsigned char	P0CFGB	@ 0x4F0;	/* Port 0 configuration B */
+static unsigned char	P1CFGB	@ 0x4F1;	/* Port 1 configuration B */
+static unsigned char	P2CFGB	@ 0x4F2;	/* Port 2 configuration B */
+static unsigned char	P3CFGB	@ 0x4F3;	/* Port 3 configuration B */
+
+static bit		ETI1	@ 0x33B;		/* TX interrupt enable 1 */
+static bit		ERI1	@ 0x33A;		/* RX interrupt enable 1 */
+static bit		ETI0	@ 0x339;		/* TX interrupt enable 0 */
+static bit		ERI0	@ 0x338;		/* RX interrupt enable 0 */
+static bit		EA	@ 0x337;		/* global int. enable */
+static bit		ET2	@ 0x334;		/* timer 2 interrupt */
+static bit		ET1	@ 0x333;		/* timer 1 interrupt */
+static bit		EX1	@ 0x332;		/* external interrupt 1 */
+static bit		ET0	@ 0x331;		/* timer 0 interrupt */
+static bit		EX0	@ 0x330;		/* external interrupt 0 */
+static bit		PD	@ 0x221;		/* power down */
+static bit		IDL	@ 0x220;
+static bit		SM	@ 0x20F;
+static bit		TM	@ 0x20E;
+static bit		RS1	@ 0x20D;
+static bit		RS0	@ 0x20C;
+static bit		IM3	@ 0x20B;
+static bit		IM2	@ 0x20A;
+static bit		IM1	@ 0x209;
+static bit		IM0	@ 0x208;
+static bit		S0M0	@ 0x307;
+static bit		S0M1	@ 0x306;
+static bit		S0M2	@ 0x305;
+static bit		R0EN	@ 0x304;
+static bit		T0B8	@ 0x303;
+static bit		R0B8	@ 0x302;
+static bit		TI0	@ 0x301;		/* serial port 0 tx ready */
+static bit		RI0	@ 0x300;		/* serial port 0 rx ready */
+static bit		FE0	@ 0x30B;
+static bit		BR0	@ 0x30A;
+static bit		OE0	@ 0x309;
+static bit		STINT0	@ 0x308;
+static bit		S1M0	@ 0x327;
+static bit		S1M1	@ 0x326;
+static bit		S1M2	@ 0x325;
+static bit		R1EN	@ 0x324;
+static bit		T1B8	@ 0x323;
+static bit		R1B8	@ 0x322;
+static bit		TI1	@ 0x321;		/* serial port 0 tx ready */
+static bit		RI1	@ 0x320;		/* serial port 0 rx ready */
+static bit		FE1	@ 0x32B;
+static bit		BR1	@ 0x32A;
+static bit		OE1	@ 0x329;
+static bit		STINT1	@ 0x328;
+static bit		SWR7	@ 0x356;
+static bit		SWR6	@ 0x355;
+static bit		SWR5	@ 0x354;
+static bit		SWR4	@ 0x353;
+static bit		SWR3	@ 0x352;
+static bit		SWR2	@ 0x351;
+static bit		SWR1	@ 0x350;
+static bit		TF2	@ 0x2C7;
+static bit		EXF2	@ 0x2C6;
+static bit		RCLK0	@ 0x2C5;
+static bit		TCLK0	@ 0x2C4;
+static bit		RCLK1	@ 0x2CD;
+static bit		TCLK1	@ 0x2CC;
+static bit		EXEN2	@ 0x2C3;
+static bit		TR2	@ 0x2C2;
+static bit		CT2	@ 0x2C1;
+static bit		CPRL2	@ 0x2C0;
+static bit		T2OE	@ 0x2C9;
+static bit		DCEN	@ 0x2C8;
+static bit		TF1	@ 0x287;
+static bit		TR1	@ 0x286;
+static bit		TF0	@ 0x285;
+static bit		TR0	@ 0x284;
+static bit		IE1	@ 0x283;
+static bit		IT1	@ 0x282;
+static bit		IE0	@ 0x281;
+static bit		IT0	@ 0x280;
+
+static bit		T1OE	@ 0x28A;
+static bit		T0OE	@ 0x288;
+static bit		PRE2	@ 0x2FF;
+static bit		PRE1	@ 0x2FE;
+static bit		PRE0	@ 0x2FD;
+static bit		WDRUN	@ 0x2FA;
+static bit		WDTOF	@ 0x2F9;
+static bit		WDMOD	@ 0x2F8;
+
+static bit		WR1	@ 0x388;
+static bit		RXD1	@ 0x38C;
+static bit		TXD1	@ 0x38D;
+static bit		T2	@ 0x38E;
+static bit		T2EX	@ 0x38F;
+static bit		RXD0	@ 0x398;
+static bit		TXD0	@ 0x399;
+static bit		INT0	@ 0x39A;
+static bit		INT1	@ 0x39B;
+static bit		T0	@ 0x39C;
+static bit		T1	@ 0x39D;
+static bit		WR	@ 0x39E;
+static bit		RD	@ 0x39F;
+
+/*
+ * Interrupt-related
+ */
+
+
+/* Vectors */
+				/* Exception vectors. */
+#define	IV_BRKPT	0x04	/* breakpoint vector */
+#define	IV_TRACE	0x08	/* Trace mode bit set */
+#define	IV_STKOVER	0x0C	/* stack overflow */
+#define	IV_DIVZERO	0x10	/* divide by zero */
+#define	IV_IRET		0x14	/* user mode IRET */
+
+#define IV_TRI0		0x40	/* Trap interrupt vectors. */
+#define IV_TRI1		0x44
+#define IV_TRI2		0x48
+#define IV_TRI3		0x4C
+#define IV_TRI4		0x50
+#define IV_TRI5		0x54
+#define IV_TRI6		0x58
+#define IV_TRI7		0x5C
+#define IV_TRI8		0x60
+#define IV_TRI9		0x64
+#define IV_TRI10	0x68
+#define IV_TRI11	0x6C
+#define IV_TRI12	0x70
+#define IV_TRI13	0x74
+#define IV_TRI14	0x78
+#define IV_TRI15	0x7C
+#define	IV_EX0		0x80	/* Event interrupt vectors. */
+#define	IV_T0		0x84
+#define	IV_EX1		0x88
+#define	IV_T1		0x8C
+#define	IV_T2		0x90
+#define	IV_RI0		0xA0
+#define	IV_TI0		0xA4
+#define	IV_RI1		0xA8
+#define	IV_TI1		0xAC
+#define	IV_SWI1		0x100	/* Software interrupt vectorss */
+#define	IV_SWI2		0x104
+#define	IV_SWI3		0x108
+#define	IV_SWI4		0x10C
+#define	IV_SWI5		0x110
+#define	IV_SWI6		0x114
+#define	IV_SWI7		0x118
+
+/* PSW Values for interrupt vectors */
+
+#define	IV_PSW		0x8F00	/* System mode, high priority, bank 0 */
+
+#define	IV_SYSTEM	0x8000
+
+#define	IV_PRI00	0x0000	/* priorities 0 - 15 */
+#define	IV_PRI01	0x0100
+#define	IV_PRI02	0x0200
+#define	IV_PRI03	0x0300
+#define	IV_PRI04	0x0400
+#define	IV_PRI05	0x0500
+#define	IV_PRI06	0x0600
+#define	IV_PRI07	0x0700
+#define	IV_PRI08	0x0800
+#define	IV_PRI09	0x0900
+#define	IV_PRI10	0x0A00
+#define	IV_PRI11	0x0B00
+#define	IV_PRI12	0x0C00
+#define	IV_PRI13	0x0D00
+#define	IV_PRI14	0x0E00
+#define	IV_PRI15	0x0F00
+
+#define	IV_BANK0	0x0000
+#define	IV_BANK1	0x1000
+#define	IV_BANK2	0x2000
+#define	IV_BANK3	0x3000
+
+#endif	/* __xa_h__ */

compilers/HT-XA/INCLUDE/xa-c3.h

@@ -0,0 +1,555 @@
+/*
+ *	XA-C3 SFR definitions
+ *	Extracted directly from Philips documentation
+ */
+
+#ifndef	__xa_h__
+#define	__xa_h__
+
+extern unsigned int	__trap(unsigned char, ...);
+#pragma inline(__trap)
+
+static unsigned char	M0MIDH	@ 0x000;		/* message 0 match ID high */
+static unsigned char	M0MIDL	@ 0x002;		/* message 0 match ID low */
+static unsigned char	M0MSKH	@ 0x004;		/* message 0 mask high */
+static unsigned char	M0MSKL	@ 0x006;		/* message 0 mask low */
+static unsigned char	M0CTRL	@ 0x008;		/* message 0 control */
+static unsigned char	M0BLR	@ 0x00A;		/* message 0 buffer location */
+static unsigned char	M0BSZ	@ 0x00C;		/* message 0 buffer size */
+static unsigned char	M0FCR	@ 0x00E;		/* message 0 fragmentation count */
+static unsigned char	M1MIDH	@ 0x010;		/* message 1 match ID high */
+static unsigned char	M1MIDL	@ 0x012;		/* message 1 match ID low */
+static unsigned char	M1MSKH	@ 0x014;		/* message 1 mask high */
+static unsigned char	M1MSKL	@ 0x016;		/* message 1 mask low */
+static unsigned char	M1CTRL	@ 0x018;		/* message 1 control */
+static unsigned char	M1BLR	@ 0x01A;		/* message 1 buffer location */
+static unsigned char	M1BSZ	@ 0x01C;		/* message 1 buffer size */
+static unsigned char	M1FCR	@ 0x01E;		/* message 1 fragmentation count */
+static unsigned char	M2MIDH	@ 0x020;		/* message 2 match ID high */
+static unsigned char	M2MIDL	@ 0x022;		/* message 2 match ID low */
+static unsigned char	M2MSKH	@ 0x024;		/* message 2 mask high */
+static unsigned char	M2MSKL	@ 0x026;		/* message 2 mask low */
+static unsigned char	M2CTRL	@ 0x028;		/* message 2 control */
+static unsigned char	M2BLR	@ 0x02A;		/* message 2 buffer location */
+static unsigned char	M2BSZ	@ 0x02C;		/* message 2 buffer size */
+static unsigned char	M2FCR	@ 0x02E;		/* message 2 fragmentation count */
+static unsigned char	M3MIDH	@ 0x030;		/* message 3 match ID high */
+static unsigned char	M3MIDL	@ 0x032;		/* message 3 match ID low */
+static unsigned char	M3MSKH	@ 0x034;		/* message 3 mask high */
+static unsigned char	M3MSKL	@ 0x036;		/* message 3 mask low */
+static unsigned char	M3CTRL	@ 0x038;		/* message 3 control */
+static unsigned char	M3BLR	@ 0x03A;		/* message 3 buffer location */
+static unsigned char	M3BSZ	@ 0x03C;		/* message 3 buffer size */
+static unsigned char	M3FCR	@ 0x03E;		/* message 3 fragmentation count */
+static unsigned char	M4MIDH	@ 0x040;		/* message 4 match ID high */
+static unsigned char	M4MIDL	@ 0x042;		/* message 4 match ID low */
+static unsigned char	M4MSKH	@ 0x044;		/* message 4 mask high */
+static unsigned char	M4MSKL	@ 0x046;		/* message 4 mask low */
+static unsigned char	M4CTRL	@ 0x048;		/* message 4 control */
+static unsigned char	M4BLR	@ 0x04A;		/* message 4 buffer location */
+static unsigned char	M4BSZ	@ 0x04C;		/* message 4 buffer size */
+static unsigned char	M4FCR	@ 0x04E;		/* message 4 fragmentation count */
+static unsigned char	M5MIDH	@ 0x050;		/* message 5 match ID high */
+static unsigned char	M5MIDL	@ 0x052;		/* message 5 match ID low */
+static unsigned char	M5MSKH	@ 0x054;		/* message 5 mask high */
+static unsigned char	M5MSKL	@ 0x056;		/* message 5 mask low */
+static unsigned char	M5CTRL	@ 0x058;		/* message 5 control */
+static unsigned char	M5BLR	@ 0x05A;		/* message 5 buffer location */
+static unsigned char	M5BSZ	@ 0x05C;		/* message 5 buffer size */
+static unsigned char	M5FCR	@ 0x05E;		/* message 5 fragmentation count */
+static unsigned char	M6MIDH	@ 0x060;		/* message 6 match ID high */
+static unsigned char	M6MIDL	@ 0x062;		/* message 6 match ID low */
+static unsigned char	M6MSKH	@ 0x064;		/* message 6 mask high */
+static unsigned char	M6MSKL	@ 0x066;		/* message 6 mask low */
+static unsigned char	M6CTRL	@ 0x068;		/* message 6 control */
+static unsigned char	M6BLR	@ 0x06A;		/* message 6 buffer location */
+static unsigned char	M6BSZ	@ 0x06C;		/* message 6 buffer size */
+static unsigned char	M6FCR	@ 0x06E;		/* message 6 fragmentation count */
+static unsigned char	M7MIDH	@ 0x070;		/* message 7 match ID high */
+static unsigned char	M7MIDL	@ 0x072;		/* message 7 match ID low */
+static unsigned char	M7MSKH	@ 0x074;		/* message 7 mask high */
+static unsigned char	M7MSKL	@ 0x076;		/* message 7 mask low */
+static unsigned char	M7CTRL	@ 0x078;		/* message 7 control */
+static unsigned char	M7BLR	@ 0x07A;		/* message 7 buffer location */
+static unsigned char	M7BSZ	@ 0x07C;		/* message 7 buffer size */
+static unsigned char	M7FCR	@ 0x07E;		/* message 7 fragmentation count */
+static unsigned char	M8MIDH	@ 0x080;		/* message 8 match ID high */
+static unsigned char	M8MIDL	@ 0x082;		/* message 8 match ID low */
+static unsigned char	M8MSKH	@ 0x084;		/* message 8 mask high */
+static unsigned char	M8MSKL	@ 0x086;		/* message 8 mask low */
+static unsigned char	M8CTRL	@ 0x088;		/* message 8 control */
+static unsigned char	M8BLR	@ 0x08A;		/* message 8 buffer location */
+static unsigned char	M8BSZ	@ 0x08C;		/* message 8 buffer size */
+static unsigned char	M8FCR	@ 0x08E;		/* message 8 fragmentation count */
+static unsigned char	M9MIDH	@ 0x090;		/* message 9 match ID high */
+static unsigned char	M9MIDL	@ 0x092;		/* message 9 match ID low */
+static unsigned char	M9MSKH	@ 0x094;		/* message 9 mask high */
+static unsigned char	M9MSKL	@ 0x096;		/* message 9 mask low */
+static unsigned char	M9CTRL	@ 0x098;		/* message 9 control */
+static unsigned char	M9BLR	@ 0x09A;		/* message 9 buffer location */
+static unsigned char	M9BSZ	@ 0x09C;		/* message 9 buffer size */
+static unsigned char	M9FCR	@ 0x09E;		/* message 9 fragmentation count */
+static unsigned char	M10MIDH	@ 0x0A0;		/* message 10 match ID high */
+static unsigned char	M10MIDL	@ 0x0A2;		/* message 10 match ID low */
+static unsigned char	M10MSKH	@ 0x0A4;		/* message 10 mask high */
+static unsigned char	M10MSKL	@ 0x0A6;		/* message 10 mask low */
+static unsigned char	M10CTRL	@ 0x0A8;		/* message 10 control */
+static unsigned char	M10BLR	@ 0x0AA;		/* message 10 buffer location */
+static unsigned char	M10BSZ	@ 0x0AC;		/* message 10 buffer size */
+static unsigned char	M10FCR	@ 0x0AE;		/* message 10 fragmentation count */
+static unsigned char	M11MIDH	@ 0x0B0;		/* message 11 match ID high */
+static unsigned char	M11MIDL	@ 0x0B2;		/* message 11 match ID low */
+static unsigned char	M11MSKH	@ 0x0B4;		/* message 11 mask high */
+static unsigned char	M11MSKL	@ 0x0B6;		/* message 11 mask low */
+static unsigned char	M11CTRL	@ 0x0B8;		/* message 11 control */
+static unsigned char	M11BLR	@ 0x0BA;		/* message 11 buffer location */
+static unsigned char	M11BSZ	@ 0x0BC;		/* message 11 buffer size */
+static unsigned char	M11FCR	@ 0x0BE;		/* message 11 fragmentation count */
+static unsigned char	M12MIDH	@ 0x0C0;		/* message 12 match ID high */
+static unsigned char	M12MIDL	@ 0x0C2;		/* message 12 match ID low */
+static unsigned char	M12MSKH	@ 0x0C4;		/* message 12 mask high */
+static unsigned char	M12MSKL	@ 0x0C6;		/* message 12 mask low */
+static unsigned char	M12CTRL	@ 0x0C8;		/* message 12 control */
+static unsigned char	M12BLR	@ 0x0CA;		/* message 12 buffer location */
+static unsigned char	M12BSZ	@ 0x0CC;		/* message 12 buffer size */
+static unsigned char	M12FCR	@ 0x0CE;		/* message 12 fragmentation count */
+static unsigned char	M13MIDH	@ 0x0D0;		/* message 13 match ID high */
+static unsigned char	M13MIDL	@ 0x0D2;		/* message 13 match ID low */
+static unsigned char	M13MSKH	@ 0x0D4;		/* message 13 mask high */
+static unsigned char	M13MSKL	@ 0x0D6;		/* message 13 mask low */
+static unsigned char	M13CTRL	@ 0x0D8;		/* message 13 control */
+static unsigned char	M13BLR	@ 0x0DA;		/* message 13 buffer location */
+static unsigned char	M13BSZ	@ 0x0DC;		/* message 13 buffer size */
+static unsigned char	M13FCR	@ 0x0DE;		/* message 13 fragmentation count */
+static unsigned char	M14MIDH	@ 0x0E0;		/* message 14 match ID high */
+static unsigned char	M14MIDL	@ 0x0E2;		/* message 14 match ID low */
+static unsigned char	M14MSKH	@ 0x0E4;		/* message 14 mask high */
+static unsigned char	M14MSKL	@ 0x0E6;		/* message 14 mask low */
+static unsigned char	M14CTRL	@ 0x0E8;		/* message 14 control */
+static unsigned char	M14BLR	@ 0x0EA;		/* message 14 buffer location */
+static unsigned char	M14BSZ	@ 0x0EC;		/* message 14 buffer size */
+static unsigned char	M14FCR	@ 0x0EE;		/* message 14 fragmentation count */
+static unsigned char	M15MIDH	@ 0x0F0;		/* message 15 match ID high */
+static unsigned char	M15MIDL	@ 0x0F2;		/* message 15 match ID low */
+static unsigned char	M15MSKH	@ 0x0F4;		/* message 15 mask high */
+static unsigned char	M15MSKL	@ 0x0F6;		/* message 15 mask low */
+static unsigned char	M15CTRL	@ 0x0F8;		/* message 15 control */
+static unsigned char	M15BLR	@ 0x0FA;		/* message 15 buffer location */
+static unsigned char	M15BSZ	@ 0x0FC;		/* message 15 buffer size */
+static unsigned char	M15FCR	@ 0x0FE;		/* message 15 fragmentation count */
+static unsigned char	M16MIDH	@ 0x100;		/* message 16 match ID high */
+static unsigned char	M16MIDL	@ 0x102;		/* message 16 match ID low */
+static unsigned char	M16MSKH	@ 0x104;		/* message 16 mask high */
+static unsigned char	M16MSKL	@ 0x106;		/* message 16 mask low */
+static unsigned char	M16CTRL	@ 0x108;		/* message 16 control */
+static unsigned char	M16BLR	@ 0x10A;		/* message 16 buffer location */
+static unsigned char	M16BSZ	@ 0x10C;		/* message 16 buffer size */
+static unsigned char	M16FCR	@ 0x10E;		/* message 16 fragmentation count */
+static unsigned char	M17MIDH	@ 0x110;		/* message 17 match ID high */
+static unsigned char	M17MIDL	@ 0x112;		/* message 17 match ID low */
+static unsigned char	M17MSKH	@ 0x114;		/* message 17 mask high */
+static unsigned char	M17MSKL	@ 0x116;		/* message 17 mask low */
+static unsigned char	M17CTRL	@ 0x118;		/* message 17 control */
+static unsigned char	M17BLR	@ 0x11A;		/* message 17 buffer location */
+static unsigned char	M17BSZ	@ 0x11C;		/* message 17 buffer size */
+static unsigned char	M17FCR	@ 0x11E;		/* message 17 fragmentation count */
+static unsigned char	M18MIDH	@ 0x120;		/* message 18 match ID high */
+static unsigned char	M18MIDL	@ 0x122;		/* message 18 match ID low */
+static unsigned char	M18MSKH	@ 0x124;		/* message 18 mask high */
+static unsigned char	M18MSKL	@ 0x126;		/* message 18 mask low */
+static unsigned char	M18CTRL	@ 0x128;		/* message 18 control */
+static unsigned char	M18BLR	@ 0x12A;		/* message 18 buffer location */
+static unsigned char	M18BSZ	@ 0x12C;		/* message 18 buffer size */
+static unsigned char	M18FCR	@ 0x12E;		/* message 18 fragmentation count */
+static unsigned char	M19MIDH	@ 0x130;		/* message 19 match ID high */
+static unsigned char	M19MIDL	@ 0x132;		/* message 19 match ID low */
+static unsigned char	M19MSKH	@ 0x134;		/* message 19 mask high */
+static unsigned char	M19MSKL	@ 0x136;		/* message 19 mask low */
+static unsigned char	M19CTRL	@ 0x138;		/* message 19 control */
+static unsigned char	M19BLR	@ 0x13A;		/* message 19 buffer location */
+static unsigned char	M19BSZ	@ 0x13C;		/* message 19 buffer size */
+static unsigned char	M19FCR	@ 0x13E;		/* message 19 fragmentation count */
+static unsigned char	M20MIDH	@ 0x140;		/* message 20 match ID high */
+static unsigned char	M20MIDL	@ 0x142;		/* message 20 match ID low */
+static unsigned char	M20MSKH	@ 0x144;		/* message 20 mask high */
+static unsigned char	M20MSKL	@ 0x146;		/* message 20 mask low */
+static unsigned char	M20CTRL	@ 0x148;		/* message 20 control */
+static unsigned char	M20BLR	@ 0x14A;		/* message 20 buffer location */
+static unsigned char	M20BSZ	@ 0x14C;		/* message 20 buffer size */
+static unsigned char	M20FCR	@ 0x14E;		/* message 20 fragmentation count */
+static unsigned char	M21MIDH	@ 0x150;		/* message 21 match ID high */
+static unsigned char	M21MIDL	@ 0x152;		/* message 21 match ID low */
+static unsigned char	M21MSKH	@ 0x154;		/* message 21 mask high */
+static unsigned char	M21MSKL	@ 0x156;		/* message 21 mask low */
+static unsigned char	M21CTRL	@ 0x158;		/* message 21 control */
+static unsigned char	M21BLR	@ 0x15A;		/* message 21 buffer location */
+static unsigned char	M21BSZ	@ 0x15C;		/* message 21 buffer size */
+static unsigned char	M21FCR	@ 0x15E;		/* message 21 fragmentation count */
+static unsigned char	M22MIDH	@ 0x160;		/* message 22 match ID high */
+static unsigned char	M22MIDL	@ 0x162;		/* message 22 match ID low */
+static unsigned char	M22MSKH	@ 0x164;		/* message 22 mask high */
+static unsigned char	M22MSKL	@ 0x166;		/* message 22 mask low */
+static unsigned char	M22CTRL	@ 0x168;		/* message 22 control */
+static unsigned char	M22BLR	@ 0x16A;		/* message 22 buffer location */
+static unsigned char	M22BSZ	@ 0x16C;		/* message 22 buffer size */
+static unsigned char	M22FCR	@ 0x16E;		/* message 22 fragmentation count */
+static unsigned char	M23MIDH	@ 0x170;		/* message 23 match ID high */
+static unsigned char	M23MIDL	@ 0x172;		/* message 23 match ID low */
+static unsigned char	M23MSKH	@ 0x174;		/* message 23 mask high */
+static unsigned char	M23MSKL	@ 0x176;		/* message 23 mask low */
+static unsigned char	M23CTRL	@ 0x178;		/* message 23 control */
+static unsigned char	M23BLR	@ 0x17A;		/* message 23 buffer location */
+static unsigned char	M23BSZ	@ 0x17C;		/* message 23 buffer size */
+static unsigned char	M23FCR	@ 0x17E;		/* message 23 fragmentation count */
+static unsigned char	M24MIDH	@ 0x180;		/* message 24 match ID high */
+static unsigned char	M24MIDL	@ 0x182;		/* message 24 match ID low */
+static unsigned char	M24MSKH	@ 0x184;		/* message 24 mask high */
+static unsigned char	M24MSKL	@ 0x186;		/* message 24 mask low */
+static unsigned char	M24CTRL	@ 0x188;		/* message 24 control */
+static unsigned char	M24BLR	@ 0x18A;		/* message 24 buffer location */
+static unsigned char	M24BSZ	@ 0x18C;		/* message 24 buffer size */
+static unsigned char	M24FCR	@ 0x18E;		/* message 24 fragmentation count */
+static unsigned char	M25MIDH	@ 0x190;		/* message 25 match ID high */
+static unsigned char	M25MIDL	@ 0x192;		/* message 25 match ID low */
+static unsigned char	M25MSKH	@ 0x194;		/* message 25 mask high */
+static unsigned char	M25MSKL	@ 0x196;		/* message 25 mask low */
+static unsigned char	M25CTRL	@ 0x198;		/* message 25 control */
+static unsigned char	M25BLR	@ 0x19A;		/* message 25 buffer location */
+static unsigned char	M25BSZ	@ 0x19C;		/* message 25 buffer size */
+static unsigned char	M25FCR	@ 0x19E;		/* message 25 fragmentation count */
+static unsigned char	M26MIDH	@ 0x1A0;		/* message 26 match ID high */
+static unsigned char	M26MIDL	@ 0x1A2;		/* message 26 match ID low */
+static unsigned char	M26MSKH	@ 0x1A4;		/* message 26 mask high */
+static unsigned char	M26MSKL	@ 0x1A6;		/* message 26 mask low */
+static unsigned char	M26CTRL	@ 0x1A8;		/* message 26 control */
+static unsigned char	M26BLR	@ 0x1AA;		/* message 26 buffer location */
+static unsigned char	M26BSZ	@ 0x1AC;		/* message 26 buffer size */
+static unsigned char	M26FCR	@ 0x1AE;		/* message 26 fragmentation count */
+static unsigned char	M27MIDH	@ 0x1B0;		/* message 27 match ID high */
+static unsigned char	M27MIDL	@ 0x1B2;		/* message 27 match ID low */
+static unsigned char	M27MSKH	@ 0x1B4;		/* message 27 mask high */
+static unsigned char	M27MSKL	@ 0x1B6;		/* message 27 mask low */
+static unsigned char	M27CTRL	@ 0x1B8;		/* message 27 control */
+static unsigned char	M27BLR	@ 0x1BA;		/* message 27 buffer location */
+static unsigned char	M27BSZ	@ 0x1BC;		/* message 27 buffer size */
+static unsigned char	M27FCR	@ 0x1BE;		/* message 27 fragmentation count */
+static unsigned char	M28MIDH	@ 0x1C0;		/* message 28 match ID high */
+static unsigned char	M28MIDL	@ 0x1C2;		/* message 28 match ID low */
+static unsigned char	M28MSKH	@ 0x1C4;		/* message 28 mask high */
+static unsigned char	M28MSKL	@ 0x1C6;		/* message 28 mask low */
+static unsigned char	M28CTRL	@ 0x1C8;		/* message 28 control */
+static unsigned char	M28BLR	@ 0x1CA;		/* message 28 buffer location */
+static unsigned char	M28BSZ	@ 0x1CC;		/* message 28 buffer size */
+static unsigned char	M28FCR	@ 0x1CE;		/* message 28 fragmentation count */
+static unsigned char	M29MIDH	@ 0x1D0;		/* message 29 match ID high */
+static unsigned char	M29MIDL	@ 0x1D2;		/* message 29 match ID low */
+static unsigned char	M29MSKH	@ 0x1D4;		/* message 29 mask high */
+static unsigned char	M29MSKL	@ 0x1D6;		/* message 29 mask low */
+static unsigned char	M29CTRL	@ 0x1D8;		/* message 29 control */
+static unsigned char	M29BLR	@ 0x1DA;		/* message 29 buffer location */
+static unsigned char	M29BSZ	@ 0x1DC;		/* message 29 buffer size */
+static unsigned char	M29FCR	@ 0x1DE;		/* message 29 fragmentation count */
+static unsigned char	M30MIDH	@ 0x1E0;		/* message 30 match ID high */
+static unsigned char	M30MIDL	@ 0x1E2;		/* message 30 match ID low */
+static unsigned char	M30MSKH	@ 0x1E4;		/* message 30 mask high */
+static unsigned char	M30MSKL	@ 0x1E6;		/* message 30 mask low */
+static unsigned char	M30CTRL	@ 0x1E8;		/* message 30 control */
+static unsigned char	M30BLR	@ 0x1EA;		/* message 30 buffer location */
+static unsigned char	M30BSZ	@ 0x1EC;		/* message 30 buffer size */
+static unsigned char	M30FCR	@ 0x1EE;		/* message 30 fragmentation count */
+static unsigned char	M31MIDH	@ 0x1F0;		/* message 31 match ID high */
+static unsigned char	M31MIDL	@ 0x1F2;		/* message 31 match ID low */
+static unsigned char	M31MSKH	@ 0x1F4;		/* message 31 mask high */
+static unsigned char	M31MSKL	@ 0x1F6;		/* message 31 mask low */
+static unsigned char	M31CTRL	@ 0x1F8;		/* message 31 control */
+static unsigned char	M31BLR	@ 0x1FA;		/* message 31 buffer location */
+static unsigned char	M31BSZ	@ 0x1FC;		/* message 31 buffer size */
+static unsigned char	M31FCR	@ 0x1FE;		/* message 31 fragmentation count */
+static unsigned char	MCPLL	@ 0x224;		/* message complete status flags low */
+static unsigned char	MCPLH	@ 0x226;		/* message complete status flags high */
+static unsigned char	CANINTFLG	@ 0x228;		/* CAN interrupt flag register */
+static unsigned char	MCIR	@ 0x229;		/* message complete information */
+static unsigned char	MEIR	@ 0x22A;		/* message error information */
+static unsigned char	FESTR	@ 0x22C;		/* frame error status */
+static unsigned char	FEENR	@ 0x22E;		/* frame error enable */
+static unsigned char	SPICFG	@ 0x260;		/* SPI configuration */
+static unsigned char	SPIDATA	@ 0x262;		/* SPI data */
+static unsigned char	SPICS	@ 0x263;		/* SPI control and status */
+static unsigned char	CANCMR	@ 0x270;		/* CAN core command */
+static unsigned char	CANSTR	@ 0x271;		/* CAN core status */
+static unsigned char	CANBTR	@ 0x272;		/* CAN core bus timing */
+static unsigned char	TXERC	@ 0x274;		/* tx error counter */
+static unsigned char	RXERC	@ 0x275;		/* rx error counter */
+static unsigned char	EWLR	@ 0x276;		/* error warning limit */
+static unsigned char	ECCR	@ 0x278;		/* error code capture */
+static unsigned char	ALCR	@ 0x27A;		/* arbitration lost capture */
+static unsigned char	GCTL	@ 0x27E;		/* global control */
+static unsigned char	XRAMB	@ 0x290;		/* xram base address */
+static unsigned char	MBXSR	@ 0x291;		/* message buffer and XRAM segment register */
+static unsigned char	MIFBTRL	@ 0x292;		/* MIF bus timing register low */
+static unsigned char	MIFBTRH	@ 0x293;		/* MIF bus timing register high */
+static unsigned char	PSWL	@ 0x400;		/* program status word low */
+static unsigned char	PSWH	@ 0x401;		/* program status word high */
+static unsigned char	PSW51	@ 0x402;		/* 80c51-compatible PSW */
+static unsigned char	SSEL	@ 0x403;		/* segment selection register */
+static unsigned char	PCON	@ 0x404;		/* power control register */
+static unsigned char	TCON	@ 0x410;		/* timer 0 and 1 control register */
+static unsigned char	TSTAT	@ 0x411;		/* timer 0 and 1 extended status */
+static unsigned char	T2CON	@ 0x418;		/* timer 2 control register */
+static unsigned char	T2MOD	@ 0x419;		/* timer 2 mode control */
+static unsigned char	WDCON	@ 0x41F;		/* watchdog control register */
+static unsigned char	S0CON	@ 0x420;		/* serial port 0 control register */
+static unsigned char	S0STAT	@ 0x421;		/* serial port 0 extended status */
+static unsigned char	IEL	@ 0x426;		/* interrupt enable low */
+static unsigned char	IEH	@ 0x427;		/* interrupt enable high */
+static unsigned char	SWR	@ 0x42A;		/* software interrupt request */
+static unsigned char	P0	@ 0x430;		/* port 0 */
+static unsigned char	P1	@ 0x431;		/* port 1 */
+static unsigned char	P2	@ 0x432;		/* port 2 */
+static unsigned char	P3	@ 0x433;		/* port 3 */
+static unsigned char	SCR	@ 0x440;		/* system configuration register */
+static unsigned char	DS	@ 0x441;		/* data segment */
+static unsigned char	ES	@ 0x442;		/* extra segment */
+static unsigned char	CS	@ 0x443;		/* code segment */
+static unsigned char	TL0	@ 0x450;		/* timer 0 low byte */
+static unsigned char	TH0	@ 0x451;		/* timer 0 high byte */
+static unsigned char	TL1	@ 0x452;		/* timer 1 low byte */
+static unsigned char	TH1	@ 0x453;		/* timer 1 high byte */
+static unsigned char	RTL0	@ 0x454;		/* timer 0 extended reload low byte */
+static unsigned char	RTH0	@ 0x455;		/* timer 0 extended reload high byte */
+static unsigned char	RTL1	@ 0x456;		/* timer 1 extended reload low byte */
+static unsigned char	RTH1	@ 0x457;		/* timer 1 extended reload high byte */
+static unsigned char	TL2	@ 0x458;		/* timer 2 low byte */
+static unsigned char	TH2	@ 0x459;		/* timer 2 high byte */
+static unsigned char	T2CAPL	@ 0x45A;		/* timer 2 capture register, low byte */
+static unsigned char	T2CAPH	@ 0x45B;		/* timer 2 capture register, high byte */
+static unsigned char	TMOD	@ 0x45C;		/* timer 0 and 1 mode control */
+static unsigned char	WFEED1	@ 0x45D;		/* watchdog feed 1 */
+static unsigned char	WFEED2	@ 0x45E;		/* watchdog feed 2 */
+static unsigned char	WDL	@ 0x45F;		/* watchdog timer reload */
+static unsigned char	S0BUF	@ 0x460;		/* serial port 0 buffer register */
+static unsigned char	S0ADDR	@ 0x461;		/* serial port 0 address register */
+static unsigned char	S0ADEN	@ 0x462;		/* serial port 0 address enable register */
+static unsigned char	BTRL	@ 0x468;		/* bus timing register low */
+static unsigned char	BTRH	@ 0x469;		/* bus timing register high */
+static unsigned char	BCR	@ 0x46A;		/* bus configuration register */
+static unsigned char	P0CFGA	@ 0x470;		/* port 0 configuration a */
+static unsigned char	P1CFGA	@ 0x471;		/* port 1 configuration a */
+static unsigned char	P2CFGA	@ 0x472;		/* port 2 configuration a */
+static unsigned char	P3CFGA	@ 0x473;		/* port 3 configuration a */
+static unsigned char	SWE	@ 0x47A;		/* software enable */
+static unsigned char	MIFCNTL	@ 0x495;		/* MIF control register */
+static unsigned char	MRBL	@ 0x496;		/* MMR base address low */
+static unsigned char	MRBH	@ 0x497;		/* MMR base address high */
+static unsigned char	IPA0	@ 0x4A0;		/* interrupt priotity assignment 0 */
+static unsigned char	IPA1	@ 0x4A1;		/* interrupt priotity assignment 1 */
+static unsigned char	IPA2	@ 0x4A2;		/* interrupt priotity assignment 2 */
+static unsigned char	IPA3	@ 0x4A3;		/* interrupt priotity assignment 3 */
+static unsigned char	IPA4	@ 0x4A4;		/* interrupt priotity assignment 4 */
+static unsigned char	IPA5	@ 0x4A5;		/* interrupt priotity assignment 5 */
+static unsigned char	IPA6	@ 0x4A6;		/* interrupt priotity assignment 6 */
+static unsigned char	IPA7	@ 0x4A7;		/* interrupt priotity assignment 7 */
+static unsigned char	P0CFGB	@ 0x4F0;		/* port 0 configuration b */
+static unsigned char	P1CFGB	@ 0x4F1;		/* port 1 configuration b */
+static unsigned char	P2CFGB	@ 0x4F2;		/* port 2 configuration b */
+static unsigned char	P3CFGB	@ 0x4F3;		/* port 3 configuration b */
+
+ /* Addressable Bits */
+static bit		ZERO	@ 0x200;		/* */
+static bit		NEGATIVE	@ 0x201;		/* */
+static bit		OVERFLOW	@ 0x202;		/* */
+static bit		AC	@ 0x206;		/* */
+static bit		CARRY	@ 0x207;		/* */
+static bit		IM0	@ 0x208;		/* */
+static bit		IM1	@ 0x209;		/* */
+static bit		IM2	@ 0x20A;		/* */
+static bit		IM3	@ 0x20B;		/* */
+static bit		RS0	@ 0x20C;		/* */
+static bit		RS1	@ 0x20D;		/* */
+static bit		TM	@ 0x20E;		/* */
+static bit		SM	@ 0x20F;		/* */
+static bit		P_51	@ 0x210;		/* */
+static bit		F1_51	@ 0x211;		/* */
+static bit		V_51	@ 0x212;		/* */
+static bit		RS0_51	@ 0x213;		/* */
+static bit		RS1_51	@ 0x214;		/* */
+static bit		F0_51	@ 0x215;		/* */
+static bit		AC_51	@ 0x216;		/* */
+static bit		C_51	@ 0x217;		/* */
+static bit		R0SEG	@ 0x218;		/* */
+static bit		R1SEG	@ 0x219;		/* */
+static bit		R2SEG	@ 0x21A;		/* */
+static bit		R3SEG	@ 0x21B;		/* */
+static bit		R4SEG	@ 0x21C;		/* */
+static bit		R5SEG	@ 0x21D;		/* */
+static bit		R6SEG	@ 0x21E;		/* */
+static bit		ESWEN	@ 0x21F;		/* */
+static bit		IDL	@ 0x220;		/* */
+static bit		PD	@ 0x221;		/* */
+static bit		IT0	@ 0x280;		/* */
+static bit		IE0	@ 0x281;		/* */
+static bit		IT1	@ 0x282;		/* */
+static bit		IE1	@ 0x283;		/* */
+static bit		TR0	@ 0x284;		/* */
+static bit		TF0	@ 0x285;		/* */
+static bit		TR1	@ 0x286;		/* */
+static bit		TF1	@ 0x287;		/* */
+static bit		T0OE	@ 0x288;		/* */
+static bit		T1OE	@ 0x28A;		/* */
+static bit		DCEN	@ 0x2C8;		/* */
+static bit		T2OE	@ 0x2C9;		/* */
+static bit		WDTOF	@ 0x2F9;		/* */
+static bit		WDRUN	@ 0x2FA;		/* */
+static bit		PRE0	@ 0x2FD;		/* */
+static bit		PRE1	@ 0x2FE;		/* */
+static bit		PRE2	@ 0x2FF;		/* */
+static bit		RI_0	@ 0x300;		/* */
+static bit		TI_0	@ 0x301;		/* */
+static bit		RB8_0	@ 0x302;		/* */
+static bit		TB8_0	@ 0x303;		/* */
+static bit		REN_0	@ 0x304;		/* */
+static bit		SM2_0	@ 0x305;		/* */
+static bit		SM1_0	@ 0x306;		/* */
+static bit		SM0_0	@ 0x307;		/* */
+static bit		STINT0	@ 0x308;		/* */
+static bit		OE0	@ 0x309;		/* */
+static bit		BR0	@ 0x30A;		/* */
+static bit		FE0	@ 0x30B;		/* */
+static bit		EX0	@ 0x330;		/* */
+static bit		ET0	@ 0x331;		/* */
+static bit		EX1	@ 0x332;		/* */
+static bit		ET1	@ 0x333;		/* */
+static bit		ET2	@ 0x334;		/* */
+static bit		EBUFF	@ 0x335;		/* */
+static bit		EA	@ 0x337;		/* */
+static bit		ERIO	@ 0x338;		/* */
+static bit		ETIO	@ 0x339;		/* */
+static bit		ESPI	@ 0x33B;		/* */
+static bit		ECER	@ 0x33C;		/* */
+static bit		EMER	@ 0x33D;		/* */
+static bit		EMTI	@ 0x33E;		/* */
+static bit		EMRI	@ 0x33F;		/* */
+static bit		SWR1	@ 0x350;		/* */
+static bit		SWR2	@ 0x351;		/* */
+static bit		SWR3	@ 0x352;		/* */
+static bit		SWR4	@ 0x353;		/* */
+static bit		SWR5	@ 0x354;		/* */
+static bit		SWR6	@ 0x355;		/* */
+static bit		SWR7	@ 0x356;		/* */
+static bit		A4D0	@ 0x380;		/* */
+static bit		A5D1	@ 0x381;		/* */
+static bit		A6D2	@ 0x382;		/* */
+static bit		A7D3	@ 0x383;		/* */
+static bit		A8D4	@ 0x384;		/* */
+static bit		A9D5	@ 0x385;		/* */
+static bit		A10D6	@ 0x386;		/* */
+static bit		A11D7	@ 0x387;		/* */
+static bit		WRH	@ 0x388;		/* */
+static bit		A1	@ 0x389;		/* */
+static bit		A2	@ 0x38A;		/* */
+static bit		A3	@ 0x38B;		/* */
+static bit		SPIRX	@ 0x38C;		/* */
+static bit		SPITX	@ 0x38D;		/* */
+static bit		SPICLK	@ 0x38E;		/* */
+/* alternate function */ 
+static bit		T2	@ 0x38E;		/* */
+static bit		T2EX	@ 0x38F;		/* */
+static bit		A12D8	@ 0x390;		/* */
+static bit		A13D9	@ 0x391;		/* */
+static bit		A14D10	@ 0x392;		/* */
+static bit		A15D11	@ 0x393;		/* */
+static bit		A16D12	@ 0x394;		/* */
+static bit		A17D13	@ 0x395;		/* */
+static bit		A18D14	@ 0x396;		/* */
+static bit		A19D15	@ 0x397;		/* */
+static bit		RXD0	@ 0x398;		/* */
+static bit		TXD0	@ 0x399;		/* */
+static bit		INT0	@ 0x39A;		/* */
+static bit		INT1	@ 0x39B;		/* */
+static bit		T0	@ 0x39C;		/* */
+static bit		T1	@ 0x39D;		/* */
+static bit		WRL	@ 0x39E;		/* */
+static bit		RD	@ 0x39F;		/* */
+
+/* Interrupt Vectors */
+
+/* Exception interrupt vectors */ 
+#define IV_RESET   	0x0000	/* Reset */
+#define IV_BKPNT   	0x0004	/* Breakpoint */
+#define IV_TRACE   	0x0008	/* Trace */
+#define IV_STKOVER   	0x000C	/* Stack overflow */
+#define IV_DIVZERO   	0x0010	/* Divide by zero */
+#define IV_RETI   	0x0014	/* User RETI */
+
+/* Trap interrupt vectors */ 
+#define IV_TRI0   	0x40	/* Software trap 0 */
+#define IV_TRI1   	0x44	/* Software trap 1 */
+#define IV_TRI2   	0x48	/* Software trap 2 */
+#define IV_TRI3   	0x4C	/* Software trap 3 */
+#define IV_TRI4   	0x50	/* Software trap 4 */
+#define IV_TRI5   	0x54	/* Software trap 5 */
+#define IV_TRI6   	0x58	/* Software trap 6 */
+#define IV_TRI7   	0x5C	/* Software trap 7 */
+#define IV_TRI8   	0x60	/* Software trap 8 */
+#define IV_TRI9   	0x64	/* Software trap 9 */
+#define IV_TRI10   	0x68	/* Software trap 10 */
+#define IV_TRI11   	0x6C	/* Software trap 11 */
+#define IV_TRI12   	0x70	/* Software trap 12 */
+#define IV_TRI13   	0x74	/* Software trap 13 */
+#define IV_TRI14   	0x78	/* Software trap 14 */
+#define IV_TRI15   	0x7C	/* Software trap 15 */
+
+/* Event interrupt vectors */ 
+#define IV_EX0   	0x80	/* External interrupt 0 */
+#define IV_T0   	0x84	/* Timer 0 interrupt */
+#define IV_EX1   	0x88	/* External interrupt 1 */
+#define IV_T1   	0x8C	/* timer 1 interrupt */
+#define IV_T2   	0x90	/* timer 2 interrupt */
+#define IV_RXFULL   	0x94	/* (CAN) Rx buffer full */
+#define IV_RI0   	0xA0	/* Serial port 0 Rx */
+#define IV_TI0   	0xA4	/* Serial port 0 Tx */
+#define IV_SPI   	0xAC	/* SPI interrupt */
+#define IV_FERR   	0xB0	/* (CAN) Frame error */
+#define IV_MERR   	0xB4	/* (CAN) Message error */
+#define IV_TXDONE   	0xB8	/* Tx message complete */
+#define IV_RXDONE   	0xBC	/* Rx message complete */
+
+/* Software interrupt vectors */ 
+#define IV_SWI1   	0x100	/* Software interrupt 1 */
+#define IV_SWI2   	0x104	/* Software interrupt 2 */
+#define IV_SWI3   	0x108	/* Software interrupt 3 */
+#define IV_SWI4   	0x10C	/* Software interrupt 4 */
+#define IV_SWI5   	0x110	/* Software interrupt 5 */
+#define IV_SWI6   	0x114	/* Software interrupt 6 */
+#define IV_SWI7   	0x118	/* Software interrupt 7 */
+
+/* PSW Values for interrupt vectors */
+
+#define	IV_PSW		0x8F00	/* System mode, high priority, bank 0 */
+
+#define	IV_SYSTEM	0x8000
+
+#define	IV_PRI00	0x0000	/* priorities 0 - 15 */
+#define	IV_PRI01	0x0100
+#define	IV_PRI02	0x0200
+#define	IV_PRI03	0x0300
+#define	IV_PRI04	0x0400
+#define	IV_PRI05	0x0500
+#define	IV_PRI06	0x0600
+#define	IV_PRI07	0x0700
+#define	IV_PRI08	0x0800
+#define	IV_PRI09	0x0900
+#define	IV_PRI10	0x0A00
+#define	IV_PRI11	0x0B00
+#define	IV_PRI12	0x0C00
+#define	IV_PRI13	0x0D00
+#define	IV_PRI14	0x0E00
+#define	IV_PRI15	0x0F00
+
+#define	IV_BANK0	0x0000
+#define	IV_BANK1	0x1000
+#define	IV_BANK2	0x2000
+#define	IV_BANK3	0x3000
+
+#endif	/* __xa_h__ */
+

compilers/HT-XA/INCLUDE/xa-g3.h

@@ -0,0 +1,247 @@
+/*
+ *	XA G3 SFR definitions
+ *	Extracted directly from Philips documentation
+ */
+
+#ifndef	__xa_h__
+#define	__xa_h__
+
+extern unsigned int	__trap(unsigned char, ...);
+#pragma inline(__trap)
+
+static unsigned short	PSW	@ 0x400;	/* Program status word */
+static unsigned char	PSWL	@ 0x400;	/* Program status word (low byte) */
+static unsigned char	PSWH	@ 0x401;	/* Program status word (high byte) */
+static unsigned char	PSW51	@ 0x402;	/* 80C51 compatible PSW */
+static unsigned char	SSEL	@ 0x403;	/* Segment selection register */
+static unsigned char	PCON	@ 0x404;	/* Power control register */
+static unsigned char	TCON	@ 0x410;	/* Timer 0 and 1 control register */
+static unsigned char	TSTAT	@ 0x411;	/* Timer 0 and 1 extended status */
+static unsigned char	T2CON	@ 0x418;	/* Timer 2 control register */
+static unsigned char	T2MOD	@ 0x419;	/* Timer 2 mode control */
+static unsigned char	WDCON	@ 0x41F;	/* Watchdog control register */
+static unsigned char	S0CON	@ 0x420;	/* Serial port 0 control register */
+static unsigned char	S0STAT	@ 0x421;	/* Serial port 0 extended status */
+static unsigned char	S1CON	@ 0x424;	/* Serial port 1 control register */
+static unsigned char	S1STAT	@ 0x425;	/* Serial port 1 extended status */
+static unsigned char	IEL	@ 0x426;	/* Interrupt enable low byte */
+static unsigned char	IEH	@ 0x427;	/* Interrupt enable high byte */
+static unsigned char	SWR	@ 0x42A;	/* Software Interrupt Request */
+static unsigned char	P0	@ 0x430;	/* Port 0 */
+static unsigned char	P1	@ 0x431;	/* Port 1 */
+static unsigned char	P2	@ 0x432;	/* Port 2 */
+static unsigned char	P3	@ 0x433;	/* Port3 */
+static unsigned char	SCR	@ 0x440;	/* System configuration register */
+static unsigned char	DS	@ 0x441;	/* Data segment */
+static unsigned char	ES	@ 0x442;	/* Extra segment */
+static unsigned char	CS	@ 0x443;	/* Code segment */
+static unsigned char	TL0	@ 0x450;	/* Timer 0 low byte */
+static unsigned char	TH0	@ 0x451;	/* Timer 0 high byte */
+static unsigned char	TL1	@ 0x452;	/* Timer 1 low byte */
+static unsigned char	TH1	@ 0x453;	/* Timer 1 high byte */
+static unsigned char	RTL0	@ 0x454;	/* Timer 0 extended reload, low byte */
+static unsigned char	RTH0	@ 0x455;	/* Timer 0 extended reload, high byte */
+static unsigned char	RTL1	@ 0x456;	/* Timer 1 extended reload, low byte */
+static unsigned char	RTH1	@ 0x457;	/* Timer 1 extended reload, high byte */
+static unsigned char	TL2	@ 0x458;	/* Timer 2 low byte */
+static unsigned char	TH2	@ 0x459;	/* Timer 2 high byte */
+static unsigned char	T2CAPL	@ 0x45A;	/* Timer 2 capture register, low byte */
+static unsigned char	T2CAPH	@ 0x45B;	/* Timer 2 capture register, high byte */
+static unsigned char	TMOD	@ 0x45C;	/* Timer 0 and 1 mode register */
+static unsigned char	WFEED1	@ 0x45D;	/* Watchdog feed 1 */
+static unsigned char	WFEED2	@ 0x45E;	/* Watchdog feed 2 */
+static unsigned char	WDL	@ 0x45F;	/* Watchdog timer reload */
+static unsigned char	S0BUF	@ 0x460;	/* Serial port 0 buffer register */
+static unsigned char	S0ADDR	@ 0x461;	/* Serial port 0 address register */
+static unsigned char	S0ADEN	@ 0x462;	/* Serial port 0 address enable register */
+static unsigned char	S1BUF	@ 0x464;	/* Serial port 1 buffer register */
+static unsigned char	S1ADDR	@ 0x465;	/* Serial port 1 address register */
+static unsigned char	S1ADEN	@ 0x466;	/* Serial port 1 address enable register */
+static unsigned char	BTRL	@ 0x468;	/* Bus timing register high byte */
+static unsigned char	BTRH	@ 0x469;	/* Bus timing register low byte */
+static unsigned char	BCR	@ 0x46A;	/* Bus configuration register */
+static unsigned char	P0CFGA	@ 0x470;	/* Port 0 configuration A */
+static unsigned char	P1CFGA	@ 0x471;	/* Port 1 configuration A */
+static unsigned char	P2CFGA	@ 0x472;	/* Port 2 configuration A */
+static unsigned char	P3CFGA	@ 0x473;	/* Port 3 configuration A */
+static unsigned char	SWE	@ 0x47A;	/* Software Interrupt Enable */
+static unsigned char	IPA0	@ 0x4A0;	/* Interrupt priority 0 */
+static unsigned char	IPA1	@ 0x4A1;	/* Interrupt priority 1 */
+static unsigned char	IPA2	@ 0x4A2;	/* Interrupt priority 2 */
+static unsigned char	IPA4	@ 0x4A4;	/* Interrupt priority 4 */
+static unsigned char	IPA5	@ 0x4A5;	/* Interrupt priority 5 */
+static unsigned char	P0CFGB	@ 0x4F0;	/* Port 0 configuration B */
+static unsigned char	P1CFGB	@ 0x4F1;	/* Port 1 configuration B */
+static unsigned char	P2CFGB	@ 0x4F2;	/* Port 2 configuration B */
+static unsigned char	P3CFGB	@ 0x4F3;	/* Port 3 configuration B */
+
+static bit		ETI1	@ 0x33B;		/* TX interrupt enable 1 */
+static bit		ERI1	@ 0x33A;		/* RX interrupt enable 1 */
+static bit		ETI0	@ 0x339;		/* TX interrupt enable 0 */
+static bit		ERI0	@ 0x338;		/* RX interrupt enable 0 */
+static bit		EA	@ 0x337;		/* global int. enable */
+static bit		ET2	@ 0x334;		/* timer 2 interrupt */
+static bit		ET1	@ 0x333;		/* timer 1 interrupt */
+static bit		EX1	@ 0x332;		/* external interrupt 1 */
+static bit		ET0	@ 0x331;		/* timer 0 interrupt */
+static bit		EX0	@ 0x330;		/* external interrupt 0 */
+static bit		PD	@ 0x221;		/* power down */
+static bit		IDL	@ 0x220;
+static bit		SM	@ 0x20F;
+static bit		TM	@ 0x20E;
+static bit		RS1	@ 0x20D;
+static bit		RS0	@ 0x20C;
+static bit		IM3	@ 0x20B;
+static bit		IM2	@ 0x20A;
+static bit		IM1	@ 0x209;
+static bit		IM0	@ 0x208;
+static bit		S0M0	@ 0x307;
+static bit		S0M1	@ 0x306;
+static bit		S0M2	@ 0x305;
+static bit		R0EN	@ 0x304;
+static bit		T0B8	@ 0x303;
+static bit		R0B8	@ 0x302;
+static bit		TI0	@ 0x301;		/* serial port 0 tx ready */
+static bit		RI0	@ 0x300;		/* serial port 0 rx ready */
+static bit		FE0	@ 0x30B;
+static bit		BR0	@ 0x30A;
+static bit		OE0	@ 0x309;
+static bit		STINT0	@ 0x308;
+static bit		S1M0	@ 0x327;
+static bit		S1M1	@ 0x326;
+static bit		S1M2	@ 0x325;
+static bit		R1EN	@ 0x324;
+static bit		T1B8	@ 0x323;
+static bit		R1B8	@ 0x322;
+static bit		TI1	@ 0x321;		/* serial port 0 tx ready */
+static bit		RI1	@ 0x320;		/* serial port 0 rx ready */
+static bit		FE1	@ 0x32B;
+static bit		BR1	@ 0x32A;
+static bit		OE1	@ 0x329;
+static bit		STINT1	@ 0x328;
+static bit		SWR7	@ 0x356;
+static bit		SWR6	@ 0x355;
+static bit		SWR5	@ 0x354;
+static bit		SWR4	@ 0x353;
+static bit		SWR3	@ 0x352;
+static bit		SWR2	@ 0x351;
+static bit		SWR1	@ 0x350;
+static bit		TF2	@ 0x2C7;
+static bit		EXF2	@ 0x2C6;
+static bit		RCLK0	@ 0x2C5;
+static bit		TCLK0	@ 0x2C4;
+static bit		RCLK1	@ 0x2CD;
+static bit		TCLK1	@ 0x2CC;
+static bit		EXEN2	@ 0x2C3;
+static bit		TR2	@ 0x2C2;
+static bit		CT2	@ 0x2C1;
+static bit		CPRL2	@ 0x2C0;
+static bit		T2OE	@ 0x2C9;
+static bit		DCEN	@ 0x2C8;
+static bit		TF1	@ 0x287;
+static bit		TR1	@ 0x286;
+static bit		TF0	@ 0x285;
+static bit		TR0	@ 0x284;
+static bit		IE1	@ 0x283;
+static bit		IT1	@ 0x282;
+static bit		IE0	@ 0x281;
+static bit		IT0	@ 0x280;
+
+static bit		T1OE	@ 0x28A;
+static bit		T0OE	@ 0x288;
+static bit		PRE2	@ 0x2FF;
+static bit		PRE1	@ 0x2FE;
+static bit		PRE0	@ 0x2FD;
+static bit		WDRUN	@ 0x2FA;
+static bit		WDTOF	@ 0x2F9;
+static bit		WDMOD	@ 0x2F8;
+
+static bit		WR1	@ 0x388;
+static bit		RXD1	@ 0x38C;
+static bit		TXD1	@ 0x38D;
+static bit		T2	@ 0x38E;
+static bit		T2EX	@ 0x38F;
+static bit		RXD0	@ 0x398;
+static bit		TXD0	@ 0x399;
+static bit		INT0	@ 0x39A;
+static bit		INT1	@ 0x39B;
+static bit		T0	@ 0x39C;
+static bit		T1	@ 0x39D;
+static bit		WR	@ 0x39E;
+static bit		RD	@ 0x39F;
+
+/*
+ * Interrupt-related
+ */
+
+
+/* Vectors */
+				/* Exception vectors. */
+#define	IV_BRKPT	0x04	/* breakpoint vector */
+#define	IV_TRACE	0x08	/* Trace mode bit set */
+#define	IV_STKOVER	0x0C	/* stack overflow */
+#define	IV_DIVZERO	0x10	/* divide by zero */
+#define	IV_IRET		0x14	/* user mode IRET */
+
+#define IV_TRI0		0x40	/* Trap interrupt vectors. */
+#define IV_TRI1		0x44
+#define IV_TRI2		0x48
+#define IV_TRI3		0x4C
+#define IV_TRI4		0x50
+#define IV_TRI5		0x54
+#define IV_TRI6		0x58
+#define IV_TRI7		0x5C
+#define IV_TRI8		0x60
+#define IV_TRI9		0x64
+#define IV_TRI10	0x68
+#define IV_TRI11	0x6C
+#define IV_TRI12	0x70
+#define IV_TRI13	0x74
+#define IV_TRI14	0x78
+#define IV_TRI15	0x7C
+#define	IV_EX0		0x80	/* Event interrupt vectors. */
+#define	IV_T0		0x84
+#define	IV_EX1		0x88
+#define	IV_T1		0x8C
+#define	IV_T2		0x90
+#define	IV_RI0		0xA0
+#define	IV_TI0		0xA4
+#define	IV_RI1		0xA8
+#define	IV_TI1		0xAC
+#define	IV_SWI1		0x100	/* Software interrupt vectorss */
+#define	IV_SWI2		0x104
+#define	IV_SWI3		0x108
+#define	IV_SWI4		0x10C
+#define	IV_SWI5		0x110
+#define	IV_SWI6		0x114
+#define	IV_SWI7		0x118
+
+/* PSW Values for interrupt vectors */
+
+#define	IV_PSW		0x8F00	/* System mode, high priority, bank 0 */
+
+#define	IV_SYSTEM	0x8000
+
+#define	IV_PRI00	0x0000	/* priorities 0 - 15 */
+#define	IV_PRI01	0x0100
+#define	IV_PRI02	0x0200
+#define	IV_PRI03	0x0300
+#define	IV_PRI04	0x0400
+#define	IV_PRI05	0x0500
+#define	IV_PRI06	0x0600
+#define	IV_PRI07	0x0700
+#define	IV_PRI08	0x0800
+#define	IV_PRI09	0x0900
+#define	IV_PRI10	0x0A00
+#define	IV_PRI11	0x0B00
+#define	IV_PRI12	0x0C00
+#define	IV_PRI13	0x0D00
+#define	IV_PRI14	0x0E00
+#define	IV_PRI15	0x0F00
+
+#define	IV_BANK0	0x0000
+#define	IV_BANK1	0x1000
+#define	IV_BANK2	0x2000
+#define	IV_BANK3	0x3000
+
+#endif	/* __xa_h__ */

compilers/HT-XA/INCLUDE/xa-s3.h

@@ -0,0 +1,404 @@
+/*** XA-S3 SFR definitions for HiTech compiler ***/
+
+#define	__xa_h__
+
+extern unsigned int	__trap(unsigned char, ...);
+#pragma inline(__trap)
+
+static unsigned char PSWL   @ 0x400;   /* Program status word (low byte) */
+static unsigned char PSWH   @ 0x401;   /* Program status word (high byte) */
+static unsigned char PSW51  @ 0x402;   /* 80C51 compatible PSW */
+static unsigned char SSEL   @ 0x403;   /* Segment selection register */
+static unsigned char PCON   @ 0x404;   /* Power control register */
+static unsigned char TCON   @ 0x410;   /* Timer 0 and 1 control register */
+static unsigned char TSTAT  @ 0x411;   /* Timer 0 and 1 extended status */
+static unsigned char T2CON  @ 0x418;   /* Timer 2 control register */
+static unsigned char T2MOD  @ 0x419;   /* Timer 2 mode control */
+static unsigned char CCON   @ 0x41A;   /* PCA counter control */
+static unsigned char WDCON  @ 0x41F;   /* Watchdog control register */
+static unsigned char S0CON  @ 0x420;   /* Serial port 0 control register */
+static unsigned char S0STAT @ 0x421;   /* Serial port 0 extended status */
+static unsigned char S1CON  @ 0x424;   /* Serial port 1 control register */
+static unsigned char S1STAT @ 0x425;   /* Serial port 1 extended status */
+static unsigned char IEL    @ 0x426;   /* Interrupt enable low byte */
+static unsigned char IEH    @ 0x427;   /* Interrupt enable high byte */
+static unsigned char SWR    @ 0x42A;   /* Software Interrupt Request */
+static unsigned char I2CON  @ 0x42C;   /* I2C control register */
+static unsigned char IELB   @ 0x42E;   /* Int. enable extension low byte */
+static unsigned char P0     @ 0x430;   /* Port 0 */
+static unsigned char P1     @ 0x431;   /* Port 1 */
+static unsigned char P2     @ 0x432;   /* Port 2 */
+static unsigned char P3     @ 0x433;   /* Port 3 */
+static unsigned char P4     @ 0x434;   /* Port 4 */
+static unsigned char P5     @ 0x435;   /* Port 5 */
+static unsigned char P6     @ 0x436;   /* Port 6 */
+static unsigned char ADCON  @ 0x43E;   /* A/D control register */
+static unsigned char ADCS   @ 0x43F;   /* A/D channel select register */
+static unsigned char SCR    @ 0x440;   /* System configuration register */
+static unsigned char DS     @ 0x441;   /* Data segment */
+static unsigned char ES     @ 0x442;   /* Extra segment */
+static unsigned char CS     @ 0x443;   /* Code segment */
+static unsigned char TL0    @ 0x450;   /* Timer 0 low byte */
+static unsigned char TH0    @ 0x451;   /* Timer 0 high byte */
+static unsigned char TL1    @ 0x452;   /* Timer 1 low byte */
+static unsigned char TH1    @ 0x453;   /* Timer 1 high byte */
+static unsigned char RTL0   @ 0x454;   /* Timer 0 reload, low byte */
+static unsigned char RTH0   @ 0x455;   /* Timer 0 reload, high byte */
+static unsigned char RTL1   @ 0x456;   /* Timer 1 reload, low byte */
+static unsigned char RTH1   @ 0x457;   /* Timer 1 reload, high byte */
+static unsigned char TL2    @ 0x458;   /* Timer 2 low byte */
+static unsigned char TH2    @ 0x459;   /* Timer 2 high byte */
+static unsigned char T2CAPL @ 0x45A;   /* Timer 2 capture reg, low byte */
+static unsigned char T2CAPH @ 0x45B;   /* Timer 2 capture reg, high byte */
+static unsigned char TMOD   @ 0x45C;   /* Timer 0 and 1 mode control */
+static unsigned char WFEED1 @ 0x45D;   /* Watchdog feed 1 */
+static unsigned char WFEED2 @ 0x45E;   /* Watchdog feed 2 */
+static unsigned char WDL    @ 0x45F;   /* Watchdog timer reload */
+static unsigned char S0BUF  @ 0x460;   /* uart 0 buffer register */
+static unsigned char S0ADDR @ 0x461;   /* uart 0 address register */
+static unsigned char S0ADEN @ 0x462;   /* uart 0 address enable register */
+static unsigned char RSTSRC @ 0x463;   /* Reset source register */
+static unsigned char S1BUF  @ 0x464;   /* uart 1 buffer register */
+static unsigned char S1ADDR @ 0x465;   /* uart 1 address register */
+static unsigned char S1ADEN @ 0x466;   /* uart 1 address enable register */
+static unsigned char BTRL   @ 0x468;   /* Bus timing register low byte */
+static unsigned char BTRH   @ 0x469;   /* Bus timing register high byte */
+static unsigned char BCR    @ 0x46A;   /* Bus configuration register */
+static unsigned char I2STAT @ 0x46C;   /* I2C status register */
+static unsigned char I2DAT  @ 0x46D;   /* I2C data register */
+static unsigned char I2ADDR @ 0x46E;   /* I2C address register */
+static unsigned char P0CFGA @ 0x470;   /* Port 0 configuration A */
+static unsigned char P1CFGA @ 0x471;   /* Port 1 configuration A */
+static unsigned char P2CFGA @ 0x472;   /* Port 2 configuration A */
+static unsigned char P3CFGA @ 0x473;   /* Port 3 configuration A */
+static unsigned char P4CFGA @ 0x474;   /* Port 4 configuration A */
+static unsigned char P5CFGA @ 0x475;   /* Port 5 configuration A */
+static unsigned char P6CFGA @ 0x476;   /* Port 6 configuration A */
+static unsigned char SWE    @ 0x47A;   /* Software Interrupt Enable */
+static unsigned char CL     @ 0x48A;   /* PCA counter low byte */
+static unsigned char CH     @ 0x48B;   /* PCA counter high byte */
+static unsigned char CMOD   @ 0x490;   /* PCA mode control */
+static unsigned char CCAPM0 @ 0x491;   /* PCA module 0 mode */
+static unsigned char CCAPM1 @ 0x492;   /* PCA module 1 mode */
+static unsigned char CCAPM2 @ 0x493;   /* PCA module 2 mode */
+static unsigned char CCAPM3 @ 0x494;   /* PCA module 3 mode */
+static unsigned char CCAPM4 @ 0x495;   /* PCA module 4 mode */
+static unsigned char CCAP0L @ 0x496;   /* PCA module 0 capture low byte */
+static unsigned char CCAP0H @ 0x497;   /* PCA module 0 capture high byte */
+static unsigned char CCAP1L @ 0x498;   /* PCA module 1 capture low byte */
+static unsigned char CCAP1H @ 0x499;   /* PCA module 1 capture high byte */
+static unsigned char CCAP2L @ 0x49A;   /* PCA module 2 capture low byte */
+static unsigned char CCAP2H @ 0x49B;   /* PCA module 2 capture high byte */
+static unsigned char CCAP3L @ 0x49C;   /* PCA module 3 capture low byte */
+static unsigned char CCAP3H @ 0x49D;   /* PCA module 3 capture high byte */
+static unsigned char CCAP4L @ 0x49E;   /* PCA module 4 capture low byte */
+static unsigned char CCAP4H @ 0x49F;   /* PCA module 4 capture high byte */
+static unsigned char IPA0   @ 0x4A0;   /* Interrupt priority A0 */
+static unsigned char IPA1   @ 0x4A1;   /* Interrupt priority A1 */
+static unsigned char IPA2   @ 0x4A2;   /* Interrupt priority A2 */
+static unsigned char IPA3   @ 0x4A3;   /* Interrupt priority A3 */
+static unsigned char IPA4   @ 0x4A4;   /* Interrupt priority A4 */
+static unsigned char IPA5   @ 0x4A5;   /* Interrupt priority A5 */
+static unsigned char IPB0   @ 0x4A8;   /* Interrupt priority B0 */
+static unsigned char IPB1   @ 0x4A9;   /* Interrupt priority B1 */
+static unsigned char IPB2   @ 0x4AA;   /* Interrupt priority B2 */
+static unsigned char ADRSH0 @ 0x4B0;   /* A/D high byte result channel 0 */
+static unsigned char ADRSH1 @ 0x4B1;   /* A/D high byte result channel 1 */
+static unsigned char ADRSH2 @ 0x4B2;   /* A/D high byte result channel 2 */
+static unsigned char ADRSH3 @ 0x4B3;   /* A/D high byte result channel 3 */
+static unsigned char ADRSH4 @ 0x4B4;   /* A/D high byte result channel 4 */
+static unsigned char ADRSH5 @ 0x4B5;   /* A/D high byte result channel 5 */
+static unsigned char ADRSH6 @ 0x4B6;   /* A/D high byte result channel 6 */
+static unsigned char ADRSH7 @ 0x4B7;   /* A/D high byte result channel 7 */
+static unsigned char ADRSL  @ 0x4B8;   /* A/D low 2 bits of result */
+static unsigned char ADCFG  @ 0x4B9;   /* A/D timing configuration */
+static unsigned char P0CFGB @ 0x4F0;   /* Port 0 configuration B */
+static unsigned char P1CFGB @ 0x4F1;   /* Port 1 configuration B */
+static unsigned char P2CFGB @ 0x4F2;   /* Port 2 configuration B */
+static unsigned char P3CFGB @ 0x4F3;   /* Port 3 configuration B */
+static unsigned char P4CFGB @ 0x4F4;   /* Port 4 configuration B */
+static unsigned char P5CFGB @ 0x4F5;   /* Port 5 configuration B */
+static unsigned char P6CFGB @ 0x4F6;   /* Port 6 configuration B */
+
+
+static bit Z       @ 0x200;     /* PSW bits */
+static bit N       @ 0x201;
+static bit V       @ 0x202;
+static bit AC      @ 0x206;
+static bit C       @ 0x207;
+static bit IM0     @ 0x208;
+static bit IM1     @ 0x209;
+static bit IM2     @ 0x20A;
+static bit IM3     @ 0x20B;
+static bit RS0     @ 0x20C;
+static bit RS1     @ 0x20D;
+static bit TM      @ 0x20E;
+static bit SM      @ 0x20F;
+static bit P       @ 0x210;
+static bit F1      @ 0x211;
+static bit F0      @ 0x215;
+
+static bit R0SEG   @ 0x218;     /* SSEL bits */
+static bit R1SEG   @ 0x219;
+static bit R2SEG   @ 0x21A;
+static bit R3SEG   @ 0x21B;
+static bit R4SEG   @ 0x21C;
+static bit R5SEG   @ 0x21D;
+static bit R6SEG   @ 0x21E;
+static bit ESWEN   @ 0x21F;
+
+static bit IDL     @ 0x220;     /* idle mode */
+static bit PD      @ 0x221;     /* power down */
+
+static bit IT0     @ 0x280;     /* Interrupt 0 level or edge select */
+static bit IE0     @ 0x281;     /* Interrupt 0 flag */
+static bit IT1     @ 0x282;     /* Interrupt 1 level or edge select */
+static bit IE1     @ 0x283;     /* Interrupt 1 flag */
+static bit TR0     @ 0x284;     /* Timer 0 run control */
+static bit TF0     @ 0x285;     /* Timer 0 overflow flag */
+static bit TR1     @ 0x286;     /* Timer 1 run control */
+static bit TF1     @ 0x287;     /* Timer 1 overflow flag */
+static bit T0OE    @ 0x288;     /* T0 pin control */
+static bit T1OE    @ 0x28A;     /* T1 pin control */
+
+static bit CPRL2   @ 0x2C0;     /* Timer 2 capture/reload flag */
+static bit CT2     @ 0x2C1;     /* Timer 2 timer/counter select */
+static bit TR2     @ 0x2C2;     /* Timer 2 run control */
+static bit EXEN2   @ 0x2C3;     /* Timer 2 external enable bit */
+static bit TCLK0   @ 0x2C4;     /* Timer 2 transmit clock flag */
+static bit RCLK0   @ 0x2C5;     /* Timer 2 receive clock flag */
+static bit EXF2    @ 0x2C6;     /* Timer 2 external flag */
+static bit TF2     @ 0x2C7;     /* Timer 2 overflow flag */
+static bit DCEN    @ 0x2C8;     /* Timer 2 count direction control */
+static bit T2OE    @ 0x2C9;     /* T2 pin control */
+static bit TCLK1   @ 0x2CC;     /* Transmit clock flag */
+static bit RCLK1   @ 0x2CD;     /* Receive clock flag */
+
+static bit CCF0    @ 0x2D0;     /* PCA channel 0 interrupt flag */
+static bit CCF1    @ 0x2D1;     /* PCA channel 1 interrupt flag */
+static bit CCF2    @ 0x2D2;     /* PCA channel 2 interrupt flag */
+static bit CCF3    @ 0x2D3;     /* PCA channel 3 interrupt flag */
+static bit CCF4    @ 0x2D4;     /* PCA channel 4 interrupt flag */
+static bit CR      @ 0x2D6;     /* PCA counter run control bit */
+static bit CF      @ 0x2D7;     /* PCA counter overflow flag */
+
+static bit WDTOF   @ 0x2F9;     /* watchdog overflow flag */
+static bit WDRUN   @ 0x2FA;     /* watchdog run */
+static bit PRE0    @ 0x2FD;     /* watchdog prescaler bit 0 */
+static bit PRE1    @ 0x2FE;     /* watchdog prescaler bit 1 */
+static bit PRE2    @ 0x2FF;     /* watchdog prescaler bit 2 */
+
+static bit RI_0    @ 0x300;     /* UART0 receive interrupt flag */
+static bit TI_0    @ 0x301;     /* UART0 transmit interrupt flag */
+static bit RB8_0   @ 0x302;     /* UART0 mode 2/3 9th received bit */
+static bit TB8_0   @ 0x303;     /* UART0 mode 2/3 9th transmit bit */
+static bit REN_0   @ 0x304;     /* UART0 receive enable */
+static bit SM2_0   @ 0x305;     /* UART0 mode select bit 2 */
+static bit SM1_0   @ 0x306;     /* UART0 mode select bit 1 */
+static bit SM0_0   @ 0x307;     /* UART0 mode select bit 0 */
+static bit STINT0  @ 0x308;     /* UART0 status interrupt enable */
+static bit OE0     @ 0x309;     /* UART0 overrun error flag */
+static bit BR0     @ 0x30A;     /* UART0 break detect flag */
+static bit FE0     @ 0x30B;     /* UART0 framing error flag */
+static bit ERR0    @ 0x30C;
+
+static bit RI_1    @ 0x320;     /* UART1 receive interrupt flag */
+static bit TI_1    @ 0x321;     /* UART1 transmit interrupt flag */
+static bit RB8_1   @ 0x322;     /* UART1 mode 2/3 9th received bit */
+static bit TB8_1   @ 0x323;     /* UART1 mode 2/3 9th transmit bit */
+static bit REN_1   @ 0x324;     /* UART1 receive enable */
+static bit SM2_1   @ 0x325;     /* UART1 mode select bit 2 */
+static bit SM1_1   @ 0x326;     /* UART1 mode select bit 1 */
+static bit SM0_1   @ 0x327;     /* UART1 mode select bit 0 */
+static bit STINT1  @ 0x328;     /* UART1 status interrupt enable */
+static bit OE1     @ 0x329;     /* UART1 overrun error flag */
+static bit BR1     @ 0x32A;     /* UART1 break detect flag */
+static bit FE1     @ 0x32B;     /* UART1 framing error flag */
+static bit ERR1    @ 0x32C;
+
+static bit EX0     @ 0x330;     /* enable external interrupt 0 */
+static bit ET0     @ 0x331;     /* enable timer 0 interrupt */
+static bit EX1     @ 0x332;     /* enable external interrupt 1 */
+static bit ET1     @ 0x333;     /* enable timer 1 interrupt */
+static bit ET2     @ 0x334;     /* enable timer 2 interrupt */
+static bit EPC     @ 0x335;     /* enable PCA interrupt */
+static bit EAD     @ 0x336;     /* enable ADC interrupt */
+static bit EA      @ 0x337;     /* global int. enable */
+static bit ERI0    @ 0x338;     /* RX 0 interrupt enable */
+static bit ETI0    @ 0x339;     /* TX 0 interrupt enable */
+static bit ERI1    @ 0x33A;     /* RX 1 interrupt enable */
+static bit ETI1    @ 0x33B;     /* TX 1 interrupt enable */
+
+static bit SWR1    @ 0x350;     /* Software interrupt bits */
+static bit SWR2    @ 0x351;
+static bit SWR3    @ 0x352;
+static bit SWR4    @ 0x353;
+static bit SWR5    @ 0x354;
+static bit SWR6    @ 0x355;
+static bit SWR7    @ 0x356;
+
+static bit CR0     @ 0x360;     /* I2C rate control bit 0 */
+static bit CR1     @ 0x361;     /* I2C rate control bit 1 */
+static bit AA      @ 0x362;     /* I2C assert acknowledge */
+static bit SI      @ 0x363;     /* I2C serial interrupt flag */
+static bit STO     @ 0x364;     /* I2C stop flag */
+static bit STA     @ 0x365;     /* I2C start flag */
+static bit ENA     @ 0x366;     /* I2C enable */
+static bit CR2     @ 0x367;     /* I2C rate control bit 2 */
+
+static bit EC0     @ 0x370;     /* enable PCA channel 0 interrupt */
+static bit EC1     @ 0x371;     /* enable PCA channel 1 interrupt */
+static bit EC2     @ 0x372;     /* enable PCA channel 2 interrupt */
+static bit EC3     @ 0x373;     /* enable PCA channel 3 interrupt */
+static bit EC4     @ 0x374;     /* enable PCA channel 4 interrupt */
+static bit EI2     @ 0x375;     /* enable I2C interrupt */
+
+static bit P0_0    @ 0x380;     /* Port 0 bits */
+static bit P0_1    @ 0x381;
+static bit P0_2    @ 0x382;
+static bit P0_3    @ 0x383;
+static bit P0_4    @ 0x384;
+static bit P0_5    @ 0x385;
+static bit P0_6    @ 0x386;
+static bit P0_7    @ 0x387;
+
+static bit P1_0    @ 0x388;     /* Port 1 bits */
+static bit P1_1    @ 0x389;
+static bit P1_2    @ 0x38A;
+static bit P1_3    @ 0x38B;
+static bit P1_4    @ 0x38C;
+static bit P1_5    @ 0x38D;
+static bit P1_6    @ 0x38E;
+static bit P1_7    @ 0x38F;
+
+static bit P2_0    @ 0x390;     /* Port 2 bits */
+static bit P2_1    @ 0x391;
+static bit P2_2    @ 0x392;
+static bit P2_3    @ 0x393;
+static bit P2_4    @ 0x394;
+static bit P2_5    @ 0x395;
+static bit P2_6    @ 0x396;
+static bit P2_7    @ 0x397;
+
+static bit P3_0    @ 0x398;     /* Port 3 bits */
+static bit P3_1    @ 0x399;
+static bit P3_2    @ 0x39A;
+static bit P3_3    @ 0x39B;
+static bit P3_4    @ 0x39C;
+static bit P3_5    @ 0x39D;
+static bit P3_6    @ 0x39E;
+static bit P3_7    @ 0x39F;
+
+static bit P4_0    @ 0x3A0;     /* Port 4 bits */
+static bit P4_1    @ 0x3A1;
+static bit P4_2    @ 0x3A2;
+static bit P4_3    @ 0x3A3;
+static bit P4_4    @ 0x3A4;
+static bit P4_5    @ 0x3A5;
+static bit P4_6    @ 0x3A6;
+static bit P4_7    @ 0x3A7;
+
+static bit P5_0    @ 0x3A8;     /* Port 5 bits */
+static bit P5_1    @ 0x3A9;
+static bit P5_2    @ 0x3AA;
+static bit P5_3    @ 0x3AB;
+static bit P5_4    @ 0x3AC;
+static bit P5_5    @ 0x3AD;
+static bit P5_6    @ 0x3AE;
+static bit P5_7    @ 0x3AF;
+
+static bit P6_0    @ 0x3B0;     /* Port 6 bits */
+static bit P6_1    @ 0x3B1;
+
+static bit ADINT   @ 0x3F0;     /* A/D conversion ready interrupt flag */
+static bit ADSST   @ 0x3F1;     /* A/D start and status */
+static bit ADMOD   @ 0x3F2;     /* A/D mode select */
+static bit ADRES   @ 0x3F3;     /* A/D 8 or 10 bit mode select */
+
+static bit ADCS0   @ 0x3F8;     /* A/D channel 0 select bit */
+static bit ADCS1   @ 0x3F9;     /* A/D channel 1 select bit */
+static bit ADCS2   @ 0x3FA;     /* A/D channel 2 select bit */
+static bit ADCS3   @ 0x3FB;     /* A/D channel 3 select bit */
+static bit ADCS4   @ 0x3FC;     /* A/D channel 4 select bit */
+static bit ADCS5   @ 0x3FD;     /* A/D channel 5 select bit */
+static bit ADCS6   @ 0x3FE;     /* A/D channel 6 select bit */
+static bit ADCS7   @ 0x3FF;     /* A/D channel 7 select bit */
+
+
+/* Exception vectors */
+#define	IV_BRKPT	0x04	/* breakpoint vector */
+#define	IV_TRACE	0x08	/* Trace mode bit set */
+#define	IV_STKOVER	0x0C	/* stack overflow */
+#define	IV_DIVZERO	0x10	/* divide by zero */
+#define	IV_IRET		0x14	/* user mode IRET */
+
+/* Trap interrupt vectors */
+#define IV_TRI0		0x40
+#define IV_TRI1		0x44
+#define IV_TRI2		0x48
+#define IV_TRI3		0x4C
+#define IV_TRI4		0x50
+#define IV_TRI5		0x54
+#define IV_TRI6		0x58
+#define IV_TRI7		0x5C
+#define IV_TRI8		0x60
+#define IV_TRI9		0x64
+#define IV_TRI10	0x68
+#define IV_TRI11	0x6C
+#define IV_TRI12	0x70
+#define IV_TRI13	0x74
+#define IV_TRI14	0x78
+#define IV_TRI15	0x7C
+
+/* Event interrupt vectors */
+#define	IV_EX0		0x80	/* External interrupt 0 */
+#define	IV_T0		0x84	/* Timer 0 interrupt */
+#define	IV_EX1		0x88	/* External interrupt 1 */
+#define	IV_T1		0x8C	/* Timer 1 interrupt */
+#define	IV_T2		0x90	/* Timer 2 interrupt */
+#define	IV_PCA		0x94	/* PCA interrupt */
+#define	IV_ADC		0x98	/* A/D interrupt */
+#define	IV_RI0		0xA0	/* Serial port 0 Rx */
+#define	IV_TI0		0xA4	/* Serial port 0 Tx */
+#define	IV_RI1		0xA8	/* Serial port 1 Rx */
+#define	IV_TI1		0xAC	/* Serial port 1 Tx */
+#define	IV_PCA0		0xC0	/* PCA channel 0 */
+#define	IV_PCA1		0xC4	/* PCA channel 1 */
+#define	IV_PCA2		0xC8	/* PCA channel 2 */
+#define	IV_PCA3		0xCC	/* PCA channel 3 */
+#define	IV_PCA4		0xD0	/* PCA channel 4 */
+#define	IV_I2C		0xD4	/* i2c interrupt */
+
+/* Software interrupt vectors */
+#define	IV_SWI1		0x100
+#define	IV_SWI2		0x104
+#define	IV_SWI3		0x108
+#define	IV_SWI4		0x10C
+#define	IV_SWI5		0x110
+#define	IV_SWI6		0x114
+#define	IV_SWI7		0x118
+
+/* PSW Values for interrupt vectors */
+#define	IV_PSW		0x8F00	/* System mode, high priority, bank 0 */
+#define	IV_SYSTEM	0x8000
+#define	IV_PRI00	0x0000	/* priorities 0 - 15 */
+#define	IV_PRI01	0x0100
+#define	IV_PRI02	0x0200
+#define	IV_PRI03	0x0300
+#define	IV_PRI04	0x0400
+#define	IV_PRI05	0x0500
+#define	IV_PRI06	0x0600
+#define	IV_PRI07	0x0700
+#define	IV_PRI08	0x0800
+#define	IV_PRI09	0x0900
+#define	IV_PRI10	0x0A00
+#define	IV_PRI11	0x0B00
+#define	IV_PRI12	0x0C00
+#define	IV_PRI13	0x0D00
+#define	IV_PRI14	0x0E00
+#define	IV_PRI15	0x0F00
+
+#define	IV_BANK0	0x0000
+#define	IV_BANK1	0x1000
+#define	IV_BANK2	0x2000
+#define	IV_BANK3	0x3000

compilers/HT-XA/LIB/S05557/USER.INF

@@ -0,0 +1,3 @@
+HI-TECH C (XA) Cross Compiler V7.72
+Serial number CXA-05557
+Licensed to JK DK-AUDIO

compilers/HT-XA/LIB/tmp/READ.ME

@@ -0,0 +1,3 @@
+This directory contains the lib which came with the compiler.
+
+

compilers/HT-XA/READ.ME

@@ -0,0 +1,98 @@
+HI-TECH C XA Compiler
+Release Notes for V7.72 patch level 1
+
+---------------------------------------------------------------------------
+
+DATE: 11 November 1997
+
+1.1 Introduction
+
+This patch incorporates a minor fix.
+
+This release (v7.72) incorporates important improvements. The
+major improvement is in memory addressing for far objects (ie. objects
+outside of the first 64k). New features include:
+
+   * Objects may be larger than 64k in size
+   * Initialised far data objects are automatically copied from ROM into
+     RAM
+
+1.2 Known Limitations
+
+There are no known limitations in this version of the compiler.
+
+1.3 Changes
+
+A list of bugs fixed between v7.72 and v7.72pl1 follows:
+
+     10 Nov 1997
+     An SSEL bit was being cleared prematurely, causing a run-time
+     error.  This has been fixed.
+
+     Files affected: cgxa.exe
+
+A list of bugs fixed between v7.71 and v7.72 follows:
+
+     28 Aug 1997
+     When using the conditional ternary operator (? :) as the second
+     argument in a function call, where the argument was of char
+     length, the compiler could not generate code.
+
+     Files affected: cgxa.exe
+
+     22 Sep 1997
+     When using pointers to far objects, erroneous assembler could be
+     produced which used the fictional lr0 register. This has been
+     fixed.
+
+     Files affected: cgxa.exe
+
+     7 Oct 1997
+     If a function which returned a 'bit' seven or more bytes of local
+     variables, the carry flag which contained the return value would
+     be modified by the add instruction used to adjust the stack
+     pointer. This has been fixed.
+
+     Files affected: cgxa.exe
+
+
+     06 Nov 1997
+     The compiler would access the wrong address when accessing an
+     element of an array, with the array being in a far structure, but
+     not the first object in the structure. This has been fixed.
+
+     Files affected: cgxa.exe
+
+A list of bugs fixed between v7.70 and v7.71 follows:
+
+     07 Jul 1997
+     (also affects all other compilers): An unterminated comment in an
+     included file would cause cpp to crash if there was a comment in
+     the includer file. This has been fixed and now generates an
+     appropriate warnings at warning levels of -1 and -2.
+     Also, setting warning levels of less than zero did not work for
+     cpp.
+
+     Files affected: cpp.exe
+
+     09 Jul 1997
+     Initialization of a local array or structure was not setting the
+     CS register when in large model. References to a complicated data
+     structure involving a structure member that was a pointer to a
+     far array caused an illegal register name to be generated.
+     Certain circumstances resulted in a register variable not being
+     loaded when required.
+
+     Files affected: cgxa.exe
+
+     Jul 1997
+     When using a far absolute variable declared in another module,
+     the code did not get the segment correct, but sets it to zero
+     when accessing the far absolute variable. This has been fixed.
+
+     Files affected: cgxa.exe
+
+---------------------------------------------------------------------------
+
+hitech@htsoft.com
+Copyright © 1997, HI-TECH Software. All rights reserved.

compilers/HT-XA/sources/RTXA--L.AS

@@ -0,0 +1,125 @@
+;
+;	Runtime startoff module for HI-TECH C
+;	Philips XA, Large model
+;
+;	Clyde Smith-Stubbs, September 1995
+;
+;	Copyright (C) 1995, HI-TECH Software
+;	All Rights Reserved
+;
+;	This software remains the property of HI-TECH SOFTWARE and is
+;	supplied under licence only. The use of this software is
+;	permitted under the terms of that licence only. Copying of
+;	this software except for the purpose of making backup or
+;	working copies for the use of the licensee on a single
+;	processor is prohibited.
+;
+	psect	vectors,ovrld,class=CODE,align=2,space=0
+	psect	text,class=CODE,align=2,space=0
+	psect	code,class=CODE,space=0
+	psect	farbss,local,class=FARBSS,space=1,reloc=65536,size=65535,space=1
+	psect	fardata,local,class=FARDATA,space=1,reloc=65536,size=65535,space=1
+	psect	rbss,size=1024,class=DATA,space=1,reloc=2
+	psect	rdata,size=1024,class=DATA,space=0,reloc=2
+	psect	rbit,bit,size=512,class=BITSEG,space=1
+	psect	bss,class=DATA,space=1,reloc=2
+	psect	data,class=DATA,space=0,reloc=2
+	psect	const,class=DATA,space=0,reloc=2
+	psect	strings,class=DATA,space=0,reloc=2
+	psect	nvram,class=DATA,space=1,reloc=2
+	psect	farnvram,class=FARNVRAM,space=1,reloc=2
+	psect	stack,space=1,reloc=2
+	psect	heap,space=1,reloc=2
+;
+	global	start,_main,_exit		;entry point, main() and exit()
+	global	__Lrbss,__Hrbss			;rbss psect bounds
+	global	__Lrbit,__Hrbit			;rbit psect bounds
+	global	__Lrdata,__Hrdata,__Brdata	;rdata psect bounds, load addr
+	global	__Lbss,__Hbss			;bss psect bounds
+	global	__Ldata,__Hstrings,__Bdata	;data/const/strings bounds, load
+	global	__Hstack			;stack address
+	global	powerup,start
+;
+	psect	vectors
+	dw	8F00h,powerup		;point RESET vector at powerup code, set system mode
+;
+;	Copyright message, and initialization code
+;
+	psect	text
+	db	"C Library Copyright (C) 1995 HI-TECH Software",0dh,0ah
+	db	"Brisbane, QLD. Australia",0dh,0ah,0,26
+	db	"$Id$"
+;
+start:
+	and.b	440h,#0FEh		;reset page zero bit
+	mov	sp,#__Hstack-2		;initialize SP
+	add	sp,#2
+;
+;	Clear the RBIT psect
+;
+	mov	r0,#((__Hrbit-__Lrbit+7)/8) & 127
+	mov	r1,#__Lrbit/8
+	call	clear
+;
+;	Clear the RBSS psect
+;
+	mov	r0,#__Hrbss-__Lrbss
+	mov	r1,#__Lrbss
+	call	clear
+;
+;	Copy the RDATA psect
+;
+	mov	r0,#__Hrdata-__Lrdata
+	mov	r1,#__Brdata
+	mov	r2,#__Lrdata
+	call	copy
+;
+;	Clear the BSS psect
+;
+	mov	r0,#__Hbss-__Lbss
+	mov	r1,#__Lbss
+	call	clear
+;
+;	Copy the DATA,CONST and STRINGS psects
+;
+	mov	r0,#__Hstrings-__Ldata
+	mov	r1,#__Bdata
+	mov	r2,#__Ldata
+	call	copy
+;
+;	Now call the main() function
+;
+	fcall	_main
+_exit:
+	br	start
+;
+;	clear:	zero "r0" bytes of memory at address "r1",
+;		does nothing if "r0" is zero.
+;
+clear:
+	cmp	r0,#0
+	beq	2f
+1:
+	movs.b	[r1+],#0	;clear 1 byte
+	djnz	r0,1b
+2:
+	ret
+;
+;	copy:	copy "r0" bytes from address "r1" to address "r2",
+;		"r1" is treated as a code pointer. does nothing
+;		if "r0" is zero.
+;
+copy:
+	cmp	r0,#0
+	beq	2f
+1:
+	movc	r3l,[r1+]	;get source byte
+	mov	[r2+],r3l	;store to destination
+	djnz	r0,1b
+2:
+	ret
+;
+	end	start
+;
+;	End of file: "$Id$"
+;

compilers/c51/Asm/C8051F000.INC

@@ -0,0 +1,212 @@
+;-----------------------------------------------------------------------------
+;	Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
+; 	All rights reserved.
+;
+;
+; 	FILE NAME  	: C8051F000.INC 
+; 	TARGET MCUs	: C8051F000, 'F001, 'F002, 'F010, 'F011, 'F012, 'F005, 'F006, 
+;                'F007, 'F015, 'F016 and 'F017
+; 	DESCRIPTION	: Register/bit definitions for the C8051F0xx product family.  
+;
+; 	REVISION 1.9 	
+;
+;-----------------------------------------------------------------------------
+;REGISTER DEFINITIONS
+;
+P0       DATA  080H   ; PORT 0
+SP       DATA  081H   ; STACK POINTER
+DPL      DATA  082H   ; DATA POINTER - LOW BYTE
+DPH      DATA  083H   ; DATA POINTER - HIGH BYTE
+PCON     DATA  087H   ; POWER CONTROL
+TCON     DATA  088H   ; TIMER CONTROL
+TMOD     DATA  089H   ; TIMER MODE
+TL0      DATA  08AH   ; TIMER 0 - LOW BYTE
+TL1      DATA  08BH   ; TIMER 1 - LOW BYTE
+TH0      DATA  08CH   ; TIMER 0 - HIGH BYTE
+TH1      DATA  08DH   ; TIMER 1 - HIGH BYTE
+CKCON    DATA  08EH   ; CLOCK CONTROL
+PSCTL    DATA  08FH   ; PROGRAM STORE R/W CONTROL
+P1       DATA  090H   ; PORT 1
+TMR3CN   DATA  091H   ; TIMER 3 CONTROL
+TMR3RLL  DATA  092H   ; TIMER 3 RELOAD REGISTER - LOW BYTE
+TMR3RLH  DATA  093H   ; TIMER 3 RELOAD REGISTER - HIGH BYTE
+TMR3L    DATA  094H   ; TIMER 3 - LOW BYTE
+TMR3H    DATA  095H   ; TIMER 3 - HIGH BYTE
+SCON     DATA  098H   ; SERIAL PORT CONTROL
+SBUF     DATA  099H   ; SERIAL PORT BUFFER
+SPI0CFG  DATA  09AH   ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
+SPI0DAT  DATA  09BH   ; SERIAL PERIPHERAL INTERFACE 0 DATA
+SPI0CKR  DATA  09DH   ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
+CPT0CN   DATA  09EH   ; COMPARATOR 0 CONTROL
+CPT1CN   DATA  09FH   ; COMPARATOR 1 CONTROL 
+P2       DATA  0A0H   ; PORT 2
+PRT0CF   DATA  0A4H   ; PORT 0 CONFIGURATION
+PRT1CF   DATA  0A5H   ; PORT 1 CONFIGURATION
+PRT2CF   DATA  0A6H   ; PORT 2 CONFIGURATION
+PRT3CF   DATA  0A7H   ; PORT 3 CONFIGURATION 
+IE       DATA  0A8H   ; INTERRUPT ENABLE
+PRT1IF   DATA  0ADH   ; PORT 1 EXTERNAL INTERRUPT FLAGS
+EMI0CN   DATA  0AFH   ; EXTERNAL MEMORY INTERFACE CONTROL
+P3       DATA  0B0H   ; PORT 3
+OSCXCN   DATA  0B1H   ; EXTERNAL OSCILLATOR CONTROL
+OSCICN   DATA  0B2H   ; INTERNAL OSCILLATOR CONTROL
+FLSCL    DATA  0B6H   ; FLASH MEMORY TIMING PRESCALER
+FLACL    DATA  0B7H   ; FLASH ACESS LIMIT 
+IP       DATA  0B8H   ; INTERRUPT PRIORITY
+AMX0CF   DATA  0BAH   ; ADC 0 MUX CONFIGURATION
+AMX0SL   DATA  0BBH   ; ADC 0 MUX CHANNEL SELECTION
+ADC0CF   DATA  0BCH   ; ADC 0 CONFIGURATION
+ADC0L    DATA  0BEH   ; ADC 0 DATA - LOW BYTE
+ADC0H    DATA  0BFH   ; ADC 0 DATA - HIGH BYTE 
+SMB0CN   DATA  0C0H   ; SMBUS 0 CONTROL
+SMB0STA  DATA  0C1H   ; SMBUS 0 STATUS
+SMB0DAT  DATA  0C2H   ; SMBUS 0 DATA 
+SMB0ADR  DATA  0C3H   ; SMBUS 0 SLAVE ADDRESS
+ADC0GTL  DATA  0C4H   ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
+ADC0GTH  DATA  0C5H   ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
+ADC0LTL  DATA  0C6H   ; ADC 0 LESS-THAN REGISTER - LOW BYTE
+ADC0LTH  DATA  0C7H   ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
+T2CON    DATA  0C8H   ; TIMER 2 CONTROL
+RCAP2L   DATA  0CAH   ; TIMER 2 CAPTURE REGISTER - LOW BYTE
+RCAP2H   DATA  0CBH   ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
+TL2      DATA  0CCH   ; TIMER 2 - LOW BYTE
+TH2      DATA  0CDH   ; TIMER 2 - HIGH BYTE
+SMB0CR   DATA  0CFH   ; SMBUS 0 CLOCK RATE
+PSW      DATA  0D0H   ; PROGRAM STATUS WORD
+REF0CN   DATA  0D1H   ; VOLTAGE REFERENCE 0 CONTROL
+DAC0L    DATA  0D2H   ; DAC 0 REGISTER - LOW BYTE
+DAC0H    DATA  0D3H   ; DAC 0 REGISTER - HIGH BYTE
+DAC0CN   DATA  0D4H   ; DAC 0 CONTROL
+DAC1L    DATA  0D5H   ; DAC 1 REGISTER - LOW BYTE
+DAC1H    DATA  0D6H   ; DAC 1 REGISTER - HIGH BYTE
+DAC1CN   DATA  0D7H   ; DAC 1 CONTROL
+PCA0CN   DATA  0D8H   ; PCA 0 COUNTER CONTROL
+PCA0MD   DATA  0D9H   ; PCA 0 COUNTER MODE
+PCA0CPM0 DATA  0DAH   ; CONTROL REGISTER FOR PCA 0 MODULE 0
+PCA0CPM1 DATA  0DBH   ; CONTROL REGISTER FOR PCA 0 MODULE 1
+PCA0CPM2 DATA  0DCH   ; CONTROL REGISTER FOR PCA 0 MODULE 2
+PCA0CPM3 DATA  0DDH   ; CONTROL REGISTER FOR PCA 0 MODULE 3
+PCA0CPM4 DATA  0DEH   ; CONTROL REGISTER FOR PCA 0 MODULE 4
+ACC      DATA  0E0H   ; ACCUMULATOR
+XBR0     DATA  0E1H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
+XBR1     DATA  0E2H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
+XBR2     DATA  0E3H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
+EIE1     DATA  0E6H   ; EXTERNAL INTERRUPT ENABLE 1
+EIE2     DATA  0E7H   ; EXTERNAL INTERRUPT ENABLE 2
+ADC0CN   DATA  0E8H   ; ADC 0 CONTROL
+PCA0L    DATA  0E9H   ; PCA 0 TIMER - LOW BYTE
+PCA0CPL0 DATA  0EAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
+PCA0CPL1 DATA  0EBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
+PCA0CPL2 DATA  0ECH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
+PCA0CPL3 DATA  0EDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
+PCA0CPL4 DATA  0EEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
+RSTSRC   DATA  0EFH   ; RESET SOURCE 
+B        DATA  0F0H   ; B REGISTER
+EIP1     DATA  0F6H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
+EIP2     DATA  0F7H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
+SPI0CN   DATA  0F8H   ; SERIAL PERIPHERAL INTERFACE 0 CONTROL 
+PCA0H    DATA  0F9H   ; PCA 0 TIMER - HIGH BYTE
+PCA0CPH0 DATA  0FAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
+PCA0CPH1 DATA  0FBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
+PCA0CPH2 DATA  0FCH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
+PCA0CPH3 DATA  0FDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
+PCA0CPH4 DATA  0FEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
+WDTCN    DATA  0FFH   ; WATCHDOG TIMER CONTROL 
+;
+;------------------------------------------------------------------------------
+;BIT DEFINITIONS
+;
+; TCON 88H
+IT0      BIT   TCON.0 ; EXT. INTERRUPT 0 TYPE
+IE0      BIT   TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
+IT1      BIT   TCON.2 ; EXT. INTERRUPT 1 TYPE
+IE1      BIT   TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
+TR0      BIT   TCON.4 ; TIMER 0 ON/OFF CONTROL
+TF0      BIT   TCON.5 ; TIMER 0 OVERFLOW FLAG
+TR1      BIT   TCON.6 ; TIMER 1 ON/OFF CONTROL
+TF1      BIT   TCON.7 ; TIMER 1 OVERFLOW FLAG
+;
+; SCON 98H
+RI       BIT   SCON.0 ; RECEIVE INTERRUPT FLAG
+TI       BIT   SCON.1 ; TRANSMIT INTERRUPT FLAG
+RB8      BIT   SCON.2 ; RECEIVE BIT 8
+TB8      BIT   SCON.3 ; TRANSMIT BIT 8
+REN      BIT   SCON.4 ; RECEIVE ENABLE
+SM2      BIT   SCON.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
+SM1      BIT   SCON.6 ; SERIAL MODE CONTROL BIT 1
+SM0      BIT   SCON.7 ; SERIAL MODE CONTROL BIT 0
+; 
+; IE A8H
+EX0      BIT   IE.0   ; EXTERNAL INTERRUPT 0 ENABLE
+ET0      BIT   IE.1   ; TIMER 0 INTERRUPT ENABLE
+EX1      BIT   IE.2   ; EXTERNAL INTERRUPT 1 ENABLE
+ET1      BIT   IE.3   ; TIMER 1 INTERRUPT ENABLE
+ES       BIT   IE.4   ; SERIAL PORT INTERRUPT ENABLE
+ET2      BIT   IE.5   ; TIMER 2 INTERRUPT ENABLE
+EA       BIT   IE.7   ; GLOBAL INTERRUPT ENABLE
+;
+; IP B8H
+PX0      BIT   IP.0   ; EXTERNAL INTERRUPT 0 PRIORITY
+PT0      BIT   IP.1   ; TIMER 0 PRIORITY
+PX1      BIT   IP.2   ; EXTERNAL INTERRUPT 1 PRIORITY
+PT1      BIT   IP.3   ; TIMER 1 PRIORITY
+PS       BIT   IP.4   ; SERIAL PORT PRIORITY
+PT2      BIT   IP.5   ; TIMER 2 PRIORITY
+;
+; SMB0CN C0H
+SMBTOE   BIT   SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
+SMBFTE   BIT   SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
+AA       BIT   SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
+SI       BIT   SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
+STO      BIT   SMB0CN.4 ; SMBUS 0 STOP FLAG
+STA      BIT   SMB0CN.5 ; SMBUS 0 START FLAG
+ENSMB    BIT   SMB0CN.6 ; SMBUS 0 ENABLE 
+;
+; T2CON C8H
+CPRL2    BIT   T2CON.0 ; CAPTURE OR RELOAD SELECT
+CT2      BIT   T2CON.1 ; TIMER OR COUNTER SELECT
+TR2      BIT   T2CON.2 ; TIMER 2 ON/OFF CONTROL
+EXEN2    BIT   T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
+TCLK     BIT   T2CON.4 ; TRANSMIT CLOCK FLAG
+RCLK     BIT   T2CON.5 ; RECEIVE CLOCK FLAG
+EXF2     BIT   T2CON.6 ; EXTERNAL FLAG
+TF2      BIT   T2CON.7 ; TIMER 2 OVERFLOW FLAG
+;
+; PSW D0H
+P        BIT   PSW.0  ; ACCUMULATOR PARITY FLAG
+F1       BIT   PSW.1  ; USER FLAG 1
+OV       BIT   PSW.2  ; OVERFLOW FLAG
+RS0      BIT   PSW.3  ; REGISTER BANK SELECT 0
+RS1      BIT   PSW.4  ; REGISTER BANK SELECT 1
+F0       BIT   PSW.5  ; USER FLAG 0
+AC       BIT   PSW.6  ; AUXILIARY CARRY FLAG
+CY       BIT   PSW.7  ; CARRY FLAG
+;
+; PCA0CN D8H
+CCF0     BIT   PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
+CCF1     BIT   PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
+CCF2     BIT   PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
+CCF3     BIT   PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
+CCF4     BIT   PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
+CR       BIT   PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
+CF       BIT   PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+;
+; ADC0CN E8H
+ADLJST   BIT   ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
+ADWINT   BIT   ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
+ADSTM0   BIT   ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
+ADSTM1   BIT   ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
+ADBUSY   BIT   ADC0CN.4 ; ADC 0 BUSY FLAG
+ADCINT   BIT   ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG 
+ADCTM    BIT   ADC0CN.6 ; ADC 0 TRACK MODE
+ADCEN    BIT   ADC0CN.7 ; ADC 0 ENABLE
+;
+; SPI0CN F8H
+SPIEN    BIT   SPI0CN.0 ; SPI 0 SPI ENABLE
+MSTEN    BIT   SPI0CN.1 ; SPI 0 MASTER ENABLE
+SLVSEL   BIT   SPI0CN.2 ; SPI 0 SLAVE SELECT
+TXBSY    BIT   SPI0CN.3 ; SPI 0 TX BUSY FLAG
+RXOVRN   BIT   SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
+MODF     BIT   SPI0CN.5 ; SPI 0 MODE FAULT FLAG
+WCOL     BIT   SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
+SPIF     BIT   SPI0CN.7 ; SPI 0 INTERRUPT FLAG

compilers/c51/Asm/C8051F020.INC

@@ -0,0 +1,234 @@
+;-----------------------------------------------------------------------------
+;	Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
+; 	All rights reserved.
+;
+;
+; 	FILE NAME  	: C8051F020.INC 
+; 	TARGET MCUs	: C8051F020, 'F021, 'F022, 'F023 
+; 	DESCRIPTION	: Register/bit definitions for the C8051F02x product family.  
+;
+; 	REVISION 1.0 	
+;
+;-----------------------------------------------------------------------------
+;REGISTER DEFINITIONS
+;
+P0       DATA  080H   ; PORT 0
+SP       DATA  081H   ; STACK POINTER
+DPL      DATA  082H   ; DATA POINTER - LOW BYTE
+DPH      DATA  083H   ; DATA POINTER - HIGH BYTE
+P4       DATA  084H   ; PORT 4
+P5       DATA  085H   ; PORT 5
+P6       DATA  086H   ; PORT 6
+PCON     DATA  087H   ; POWER CONTROL
+TCON     DATA  088H   ; TIMER CONTROL
+TMOD     DATA  089H   ; TIMER MODE
+TL0      DATA  08AH   ; TIMER 0 - LOW BYTE
+TL1      DATA  08BH   ; TIMER 1 - LOW BYTE
+TH0      DATA  08CH   ; TIMER 0 - HIGH BYTE
+TH1      DATA  08DH   ; TIMER 1 - HIGH BYTE
+CKCON    DATA  08EH   ; CLOCK CONTROL
+PSCTL    DATA  08FH   ; PROGRAM STORE R/W CONTROL
+P1       DATA  090H   ; PORT 1
+TMR3CN   DATA  091H   ; TIMER 3 CONTROL
+TMR3RLL  DATA  092H   ; TIMER 3 RELOAD REGISTER - LOW BYTE
+TMR3RLH  DATA  093H   ; TIMER 3 RELOAD REGISTER - HIGH BYTE
+TMR3L    DATA  094H   ; TIMER 3 - LOW BYTE
+TMR3H    DATA  095H   ; TIMER 3 - HIGH BYTE
+P7       DATA  096H   ; PORT 7
+SCON0    DATA  098H   ; SERIAL PORT 0 CONTROL
+SBUF0    DATA  099H   ; SERIAL PORT 0 BUFFER
+SPI0CFG  DATA  09AH   ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
+SPI0DAT  DATA  09BH   ; SERIAL PERIPHERAL INTERFACE 0 DATA
+ADC1     DATA  09CH   ; ADC 1 DATA
+SPI0CKR  DATA  09DH   ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
+CPT0CN   DATA  09EH   ; COMPARATOR 0 CONTROL
+CPT1CN   DATA  09FH   ; COMPARATOR 1 CONTROL 
+P2       DATA  0A0H   ; PORT 2
+EMI0TC   DATA  0A1H   ; EMIF TIMING CONTROL
+EMI0CF   DATA  0A3H   ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION
+P0MDOUT  DATA  0A4H   ; PORT 0 OUTPUT MODE CONFIGURATION
+P1MDOUT  DATA  0A5H   ; PORT 1 OUTPUT MODE CONFIGURATION
+P2MDOUT  DATA  0A6H   ; PORT 2 OUTPUT MODE CONFIGURATION
+P3MDOUT  DATA  0A7H   ; PORT 3 OUTPUT MODE CONFIGURATION
+IE       DATA  0A8H   ; INTERRUPT ENABLE
+SADDR0   DATA  0A9H   ; SERIAL PORT 0 SLAVE ADDRESS
+ADC1CN	DATA  0AAH   ; ADC 1 CONTROL
+ADC1CF   DATA  0ABH   ; ADC 1 ANALOG MUX CONFIGURATION
+AMX1SL   DATA  0ACH   ; ADC 1 ANALOG MUX CHANNEL SELECT
+P3IF     DATA  0ADH   ; PORT 3 EXTERNAL INTERRUPT FLAGS
+SADEN1   DATA  0AEH   ; SERIAL PORT 1 SLAVE ADDRESS MASK
+EMI0CN   DATA  0AFH   ; EXTERNAL MEMORY INTERFACE CONTROL
+P3       DATA  0B0H   ; PORT 3
+OSCXCN   DATA  0B1H   ; EXTERNAL OSCILLATOR CONTROL
+OSCICN   DATA  0B2H   ; INTERNAL OSCILLATOR CONTROL
+P74OUT   DATA  0B5H   ; PORTS 4 - 7 OUTPUT MODE
+FLSCL    DATA  0B6H   ; FLASH MEMORY TIMING PRESCALER
+FLACL    DATA  0B7H   ; FLASH ACESS LIMIT 
+IP       DATA  0B8H   ; INTERRUPT PRIORITY
+SADEN0   DATA  0B9H   ; SERIAL PORT 0 SLAVE ADDRESS MASK
+AMX0CF   DATA  0BAH   ; ADC 0 MUX CONFIGURATION
+AMX0SL   DATA  0BBH   ; ADC 0 MUX CHANNEL SELECTION
+ADC0CF   DATA  0BCH   ; ADC 0 CONFIGURATION
+P1MDIN   DATA  0BDH   ; PORT 1 INPUT MODE
+ADC0L    DATA  0BEH   ; ADC 0 DATA - LOW BYTE
+ADC0H    DATA  0BFH   ; ADC 0 DATA - HIGH BYTE 
+SMB0CN   DATA  0C0H   ; SMBUS 0 CONTROL
+SMB0STA  DATA  0C1H   ; SMBUS 0 STATUS
+SMB0DAT  DATA  0C2H   ; SMBUS 0 DATA 
+SMB0ADR  DATA  0C3H   ; SMBUS 0 SLAVE ADDRESS
+ADC0GTL  DATA  0C4H   ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
+ADC0GTH  DATA  0C5H   ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
+ADC0LTL  DATA  0C6H   ; ADC 0 LESS-THAN REGISTER - LOW BYTE
+ADC0LTH  DATA  0C7H   ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
+T2CON    DATA  0C8H   ; TIMER 2 CONTROL
+T4CON    DATA  0C9H   ; TIMER 4 CONTROL
+RCAP2L   DATA  0CAH   ; TIMER 2 CAPTURE REGISTER - LOW BYTE
+RCAP2H   DATA  0CBH   ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
+TL2      DATA  0CCH   ; TIMER 2 - LOW BYTE
+TH2      DATA  0CDH   ; TIMER 2 - HIGH BYTE
+SMB0CR   DATA  0CFH   ; SMBUS 0 CLOCK RATE
+PSW      DATA  0D0H   ; PROGRAM STATUS WORD
+REF0CN   DATA  0D1H   ; VOLTAGE REFERENCE 0 CONTROL
+DAC0L    DATA  0D2H   ; DAC 0 REGISTER - LOW BYTE
+DAC0H    DATA  0D3H   ; DAC 0 REGISTER - HIGH BYTE
+DAC0CN   DATA  0D4H   ; DAC 0 CONTROL
+DAC1L    DATA  0D5H   ; DAC 1 REGISTER - LOW BYTE
+DAC1H    DATA  0D6H   ; DAC 1 REGISTER - HIGH BYTE
+DAC1CN   DATA  0D7H   ; DAC 1 CONTROL
+PCA0CN   DATA  0D8H   ; PCA 0 COUNTER CONTROL
+PCA0MD   DATA  0D9H   ; PCA 0 COUNTER MODE
+PCA0CPM0 DATA  0DAH   ; CONTROL REGISTER FOR PCA 0 MODULE 0
+PCA0CPM1 DATA  0DBH   ; CONTROL REGISTER FOR PCA 0 MODULE 1
+PCA0CPM2 DATA  0DCH   ; CONTROL REGISTER FOR PCA 0 MODULE 2
+PCA0CPM3 DATA  0DDH   ; CONTROL REGISTER FOR PCA 0 MODULE 3
+PCA0CPM4 DATA  0DEH   ; CONTROL REGISTER FOR PCA 0 MODULE 4
+ACC      DATA  0E0H   ; ACCUMULATOR
+XBR0     DATA  0E1H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
+XBR1     DATA  0E2H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
+XBR2     DATA  0E3H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
+RCAP4L   DATA  0E4H   ; TIMER 4 CAPTURE REGISTER - LOW BYTE
+RCAP4H   DATA  0E5H   ; TIMER 4 CAPTURE REGISTER - HIGH BYTE
+EIE1     DATA  0E6H   ; EXTERNAL INTERRUPT ENABLE 1
+EIE2     DATA  0E7H   ; EXTERNAL INTERRUPT ENABLE 2
+ADC0CN   DATA  0E8H   ; ADC 0 CONTROL
+PCA0L    DATA  0E9H   ; PCA 0 TIMER - LOW BYTE
+PCA0CPL0 DATA  0EAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
+PCA0CPL1 DATA  0EBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
+PCA0CPL2 DATA  0ECH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
+PCA0CPL3 DATA  0EDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
+PCA0CPL4 DATA  0EEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
+RSTSRC   DATA  0EFH   ; RESET SOURCE 
+B        DATA  0F0H   ; B REGISTER
+SCON1    DATA  0F1H   ; SERIAL PORT 1 CONTROL
+SBUF1    DATA  0F2H   ; SERAIL PORT 1 DATA
+SADDR1   DATA  0F3H   ; SERAIL PORT 1 
+TL4      DATA  0F4H   ; TIMER 4 DATA - LOW BYTE
+TH4      DATA  0F5H   ; TIMER 4 DATA - HIGH BYTE
+EIP1     DATA  0F6H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
+EIP2     DATA  0F7H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
+SPI0CN   DATA  0F8H   ; SERIAL PERIPHERAL INTERFACE 0 CONTROL 
+PCA0H    DATA  0F9H   ; PCA 0 TIMER - HIGH BYTE
+PCA0CPH0 DATA  0FAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
+PCA0CPH1 DATA  0FBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
+PCA0CPH2 DATA  0FCH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
+PCA0CPH3 DATA  0FDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
+PCA0CPH4 DATA  0FEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
+WDTCN    DATA  0FFH   ; WATCHDOG TIMER CONTROL 
+;
+;------------------------------------------------------------------------------
+;BIT DEFINITIONS
+;
+; TCON 88H
+IT0      BIT   TCON.0 ; EXT. INTERRUPT 0 TYPE
+IE0      BIT   TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
+IT1      BIT   TCON.2 ; EXT. INTERRUPT 1 TYPE
+IE1      BIT   TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
+TR0      BIT   TCON.4 ; TIMER 0 ON/OFF CONTROL
+TF0      BIT   TCON.5 ; TIMER 0 OVERFLOW FLAG
+TR1      BIT   TCON.6 ; TIMER 1 ON/OFF CONTROL
+TF1      BIT   TCON.7 ; TIMER 1 OVERFLOW FLAG
+;
+; SCON0 98H
+RI       BIT   SCON0.0 ; RECEIVE INTERRUPT FLAG
+TI       BIT   SCON0.1 ; TRANSMIT INTERRUPT FLAG
+RB8      BIT   SCON0.2 ; RECEIVE BIT 8
+TB8      BIT   SCON0.3 ; TRANSMIT BIT 8
+REN      BIT   SCON0.4 ; RECEIVE ENABLE
+SM2      BIT   SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
+SM1      BIT   SCON0.6 ; SERIAL MODE CONTROL BIT 1
+SM0      BIT   SCON0.7 ; SERIAL MODE CONTROL BIT 0
+; 
+; IE A8H
+EX0      BIT   IE.0   ; EXTERNAL INTERRUPT 0 ENABLE
+ET0      BIT   IE.1   ; TIMER 0 INTERRUPT ENABLE
+EX1      BIT   IE.2   ; EXTERNAL INTERRUPT 1 ENABLE
+ET1      BIT   IE.3   ; TIMER 1 INTERRUPT ENABLE
+ES       BIT   IE.4   ; SERIAL PORT INTERRUPT ENABLE
+ET2      BIT   IE.5   ; TIMER 2 INTERRUPT ENABLE
+EA       BIT   IE.7   ; GLOBAL INTERRUPT ENABLE
+;
+; IP B8H
+PX0      BIT   IP.0   ; EXTERNAL INTERRUPT 0 PRIORITY
+PT0      BIT   IP.1   ; TIMER 0 PRIORITY
+PX1      BIT   IP.2   ; EXTERNAL INTERRUPT 1 PRIORITY
+PT1      BIT   IP.3   ; TIMER 1 PRIORITY
+PS       BIT   IP.4   ; SERIAL PORT PRIORITY
+PT2      BIT   IP.5   ; TIMER 2 PRIORITY
+;
+; SMB0CN C0H
+SMBTOE   BIT   SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
+SMBFTE   BIT   SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
+AA       BIT   SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
+SI       BIT   SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
+STO      BIT   SMB0CN.4 ; SMBUS 0 STOP FLAG
+STA      BIT   SMB0CN.5 ; SMBUS 0 START FLAG
+ENSMB    BIT   SMB0CN.6 ; SMBUS 0 ENABLE 
+;
+; T2CON C8H
+CPRL2    BIT   T2CON.0 ; CAPTURE OR RELOAD SELECT
+CT2      BIT   T2CON.1 ; TIMER OR COUNTER SELECT
+TR2      BIT   T2CON.2 ; TIMER 2 ON/OFF CONTROL
+EXEN2    BIT   T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
+TCLK     BIT   T2CON.4 ; TRANSMIT CLOCK FLAG
+RCLK     BIT   T2CON.5 ; RECEIVE CLOCK FLAG
+EXF2     BIT   T2CON.6 ; EXTERNAL FLAG
+TF2      BIT   T2CON.7 ; TIMER 2 OVERFLOW FLAG
+;
+; PSW D0H
+P        BIT   PSW.0  ; ACCUMULATOR PARITY FLAG
+F1       BIT   PSW.1  ; USER FLAG 1
+OV       BIT   PSW.2  ; OVERFLOW FLAG
+RS0      BIT   PSW.3  ; REGISTER BANK SELECT 0
+RS1      BIT   PSW.4  ; REGISTER BANK SELECT 1
+F0       BIT   PSW.5  ; USER FLAG 0
+AC       BIT   PSW.6  ; AUXILIARY CARRY FLAG
+CY       BIT   PSW.7  ; CARRY FLAG
+;
+; PCA0CN D8H
+CCF0     BIT   PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
+CCF1     BIT   PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
+CCF2     BIT   PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
+CCF3     BIT   PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
+CCF4     BIT   PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
+CR       BIT   PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
+CF       BIT   PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+;
+; ADC0CN E8H
+AD0LJST  BIT   ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
+AD0WINT  BIT   ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
+AD0STM0  BIT   ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
+AD0STM1  BIT   ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
+AD0BUSY  BIT   ADC0CN.4 ; ADC 0 BUSY FLAG
+AD0INT   BIT   ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG 
+AD0TM    BIT   ADC0CN.6 ; ADC 0 TRACK MODE
+AD0EN    BIT   ADC0CN.7 ; ADC 0 ENABLE
+;
+; SPI0CN F8H
+SPIEN    BIT   SPI0CN.0 ; SPI 0 SPI ENABLE
+MSTEN    BIT   SPI0CN.1 ; SPI 0 MASTER ENABLE
+SLVSEL   BIT   SPI0CN.2 ; SPI 0 SLAVE SELECT
+TXBSY    BIT   SPI0CN.3 ; SPI 0 TX BUSY FLAG
+RXOVRN   BIT   SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
+MODF     BIT   SPI0CN.5 ; SPI 0 MODE FAULT FLAG
+WCOL     BIT   SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
+SPIF     BIT   SPI0CN.7 ; SPI 0 INTERRUPT FLAG