Implement Crystal CS4235
This commit is contained in:
@@ -23,6 +23,7 @@ enum {
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AD1848_TYPE_DEFAULT = 0,
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AD1848_TYPE_DEFAULT = 0,
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AD1848_TYPE_CS4248,
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AD1848_TYPE_CS4248,
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AD1848_TYPE_CS4231,
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AD1848_TYPE_CS4231,
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AD1848_TYPE_CS4235,
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AD1848_TYPE_CS4236
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AD1848_TYPE_CS4236
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};
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};
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@@ -46,6 +47,10 @@ typedef struct {
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int16_t buffer[SOUNDBUFLEN * 2];
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int16_t buffer[SOUNDBUFLEN * 2];
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int pos;
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int pos;
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void *cram_priv,
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(*cram_write)(uint16_t addr, uint8_t val, void *priv);
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uint8_t (*cram_read)(uint16_t addr, void *priv);
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} ad1848_t;
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} ad1848_t;
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@@ -135,6 +135,8 @@ extern const device_t wss_device;
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extern const device_t ncr_business_audio_device;
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extern const device_t ncr_business_audio_device;
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/* Crystal CS423x */
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/* Crystal CS423x */
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extern const device_t cs4235_device;
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extern const device_t cs4235_onboard_device;
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extern const device_t cs4236b_device;
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extern const device_t cs4236b_device;
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extern const device_t cs4237b_device;
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extern const device_t cs4237b_device;
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extern const device_t cs4238b_device;
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extern const device_t cs4238b_device;
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@@ -16,7 +16,7 @@
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*
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*
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* Copyright 2008-2020 Sarah Walker.
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* Copyright 2008-2020 Sarah Walker.
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* Copyright 2018-2020 TheCollector1995.
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* Copyright 2018-2020 TheCollector1995.
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* Copyright 2021 RichardG.
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* Copyright 2021-2022 RichardG.
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdint.h>
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@@ -56,7 +56,7 @@ ad1848_setdma(ad1848_t *ad1848, int dma)
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void
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void
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ad1848_updatevolmask(ad1848_t *ad1848)
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ad1848_updatevolmask(ad1848_t *ad1848)
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{
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{
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if ((ad1848->type == AD1848_TYPE_CS4236) && ((ad1848->xregs[4] & 0x10) || ad1848->wten))
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if ((ad1848->type >= AD1848_TYPE_CS4235) && ((ad1848->xregs[4] & 0x10) || ad1848->wten))
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ad1848->wave_vol_mask = 0x3f;
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ad1848->wave_vol_mask = 0x3f;
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else
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else
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ad1848->wave_vol_mask = 0x7f;
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ad1848->wave_vol_mask = 0x7f;
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@@ -69,7 +69,7 @@ ad1848_updatefreq(ad1848_t *ad1848)
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double freq;
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double freq;
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uint8_t set = 0;
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uint8_t set = 0;
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if (ad1848->type == AD1848_TYPE_CS4236) {
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if (ad1848->type >= AD1848_TYPE_CS4235) {
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if (ad1848->xregs[11] & 0x20) {
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if (ad1848->xregs[11] & 0x20) {
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freq = 16934400LL;
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freq = 16934400LL;
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switch (ad1848->xregs[13]) {
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switch (ad1848->xregs[13]) {
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@@ -134,7 +134,7 @@ ad1848_read(uint16_t addr, void *priv)
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break;
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break;
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case 18: case 19:
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case 18: case 19:
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if (ad1848->type == AD1848_TYPE_CS4236) {
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if (ad1848->type >= AD1848_TYPE_CS4235) {
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if ((ad1848->xregs[4] & 0x14) == 0x14) /* FM remapping */
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if ((ad1848->xregs[4] & 0x14) == 0x14) /* FM remapping */
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ret = ad1848->xregs[ad1848->index - 12]; /* real FM volume on registers 6 and 7 */
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ret = ad1848->xregs[ad1848->index - 12]; /* real FM volume on registers 6 and 7 */
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else if (ad1848->wten && !(ad1848->xregs[4] & 0x08)) /* wavetable remapping */
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else if (ad1848->wten && !(ad1848->xregs[4] & 0x08)) /* wavetable remapping */
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@@ -142,8 +142,14 @@ ad1848_read(uint16_t addr, void *priv)
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}
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}
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break;
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break;
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case 20: case 21:
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/* Backdoor to the Control/RAM registers on CS4235. */
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if ((ad1848->type == AD1848_TYPE_CS4235) && (ad1848->xregs[18] & 0x80))
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ret = ad1848->cram_read(ad1848->index - 15, ad1848->cram_priv);
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break;
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case 23:
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case 23:
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if ((ad1848->type == AD1848_TYPE_CS4236) && (ad1848->regs[23] & 0x08)) {
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if ((ad1848->type >= AD1848_TYPE_CS4235) && (ad1848->regs[23] & 0x08)) {
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if ((ad1848->xindex & 0xfe) == 0x00) /* remapped line volume */
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if ((ad1848->xindex & 0xfe) == 0x00) /* remapped line volume */
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ret = ad1848->regs[18 + ad1848->xindex];
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ret = ad1848->regs[18 + ad1848->xindex];
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else
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else
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@@ -174,7 +180,7 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
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ad1848->index = val & 0x1f; /* cs4231a extended mode enabled */
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ad1848->index = val & 0x1f; /* cs4231a extended mode enabled */
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else
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else
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ad1848->index = val & 0x0f; /* ad1848/cs4248 mode TODO: some variants/clones DO NOT mirror, just ignore the writes? */
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ad1848->index = val & 0x0f; /* ad1848/cs4248 mode TODO: some variants/clones DO NOT mirror, just ignore the writes? */
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if (ad1848->type == AD1848_TYPE_CS4236)
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if (ad1848->type >= AD1848_TYPE_CS4235)
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ad1848->regs[23] &= ~0x08; /* clear XRAE */
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ad1848->regs[23] &= ~0x08; /* clear XRAE */
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ad1848->trd = val & 0x20;
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ad1848->trd = val & 0x20;
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ad1848->mce = val & 0x40;
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ad1848->mce = val & 0x40;
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@@ -183,7 +189,7 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
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case 1:
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case 1:
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switch (ad1848->index) {
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switch (ad1848->index) {
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case 10:
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case 10:
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if (ad1848->type != AD1848_TYPE_CS4236)
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if (ad1848->type < AD1848_TYPE_CS4235)
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break;
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break;
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/* fall-through */
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/* fall-through */
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@@ -223,7 +229,7 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
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break;
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break;
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case 18: case 19:
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case 18: case 19:
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if (ad1848->type == AD1848_TYPE_CS4236) {
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if (ad1848->type >= AD1848_TYPE_CS4235) {
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if ((ad1848->xregs[4] & 0x14) == 0x14) { /* FM remapping */
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if ((ad1848->xregs[4] & 0x14) == 0x14) { /* FM remapping */
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ad1848->xregs[ad1848->index - 12] = val; /* real FM volume on extended registers 6 and 7 */
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ad1848->xregs[ad1848->index - 12] = val; /* real FM volume on extended registers 6 and 7 */
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temp = 1;
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temp = 1;
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@@ -265,12 +271,20 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
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}
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}
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break;
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break;
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case 20: case 21:
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/* Backdoor to the Control/RAM registers on CS4235. */
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if ((ad1848->type == AD1848_TYPE_CS4235) && (ad1848->xregs[18] & 0x80)) {
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ad1848->cram_write(ad1848->index - 15, val, ad1848->cram_priv);
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val = ad1848->regs[ad1848->index];
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}
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break;
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case 22:
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case 22:
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updatefreq = 1;
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updatefreq = 1;
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break;
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break;
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case 23:
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case 23:
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if ((ad1848->type == AD1848_TYPE_CS4236) && ((ad1848->regs[12] & 0x60) == 0x60)) {
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if ((ad1848->type >= AD1848_TYPE_CS4235) && ((ad1848->regs[12] & 0x60) == 0x60)) {
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if (!(ad1848->regs[23] & 0x08)) { /* existing (not new) XRAE is clear */
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if (!(ad1848->regs[23] & 0x08)) { /* existing (not new) XRAE is clear */
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ad1848->xindex = ((val & 0x04) << 2) | (val >> 4);
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ad1848->xindex = ((val & 0x04) << 2) | (val >> 4);
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break;
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break;
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@@ -327,7 +341,7 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
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if (updatefreq)
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if (updatefreq)
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ad1848_updatefreq(ad1848);
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ad1848_updatefreq(ad1848);
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if ((ad1848->type == AD1848_TYPE_CS4231) || (ad1848->type == AD1848_TYPE_CS4236)) { /* TODO: configure CD volume for CS4248/AD1848 too */
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if (ad1848->type >= AD1848_TYPE_CS4231) { /* TODO: configure CD volume for CS4248/AD1848 too */
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temp = (ad1848->type == AD1848_TYPE_CS4231) ? 18 : 4;
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temp = (ad1848->type == AD1848_TYPE_CS4231) ? 18 : 4;
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if (ad1848->regs[temp] & 0x80)
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if (ad1848->regs[temp] & 0x80)
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ad1848->cd_vol_l = 0;
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ad1848->cd_vol_l = 0;
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@@ -474,7 +488,7 @@ ad1848_init(ad1848_t *ad1848, uint8_t type)
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ad1848->regs[8] = 0;
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ad1848->regs[8] = 0;
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ad1848->regs[9] = 0x08;
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ad1848->regs[9] = 0x08;
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ad1848->regs[10] = ad1848->regs[11] = 0;
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ad1848->regs[10] = ad1848->regs[11] = 0;
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if ((type == AD1848_TYPE_CS4248) || (type == AD1848_TYPE_CS4231) || (type == AD1848_TYPE_CS4236))
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if ((type == AD1848_TYPE_CS4248) || (type == AD1848_TYPE_CS4231) || (type >= AD1848_TYPE_CS4235))
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ad1848->regs[12] = 0x8a;
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ad1848->regs[12] = 0x8a;
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else
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else
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ad1848->regs[12] = 0xa;
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ad1848->regs[12] = 0xa;
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@@ -489,7 +503,7 @@ ad1848_init(ad1848_t *ad1848, uint8_t type)
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ad1848->regs[25] = CS4231;
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ad1848->regs[25] = CS4231;
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ad1848->regs[26] = 0x80;
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ad1848->regs[26] = 0x80;
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ad1848->regs[29] = 0x80;
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ad1848->regs[29] = 0x80;
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} else if (type == AD1848_TYPE_CS4236) {
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} else if (type >= AD1848_TYPE_CS4235) {
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ad1848->regs[16] = ad1848->regs[17] = 0;
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ad1848->regs[16] = ad1848->regs[17] = 0;
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ad1848->regs[18] = ad1848->regs[19] = 0;
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ad1848->regs[18] = ad1848->regs[19] = 0;
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ad1848->regs[20] = ad1848->regs[21] = 0;
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ad1848->regs[20] = ad1848->regs[21] = 0;
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@@ -12,7 +12,7 @@
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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* Authors: RichardG, <richardg867@gmail.com>
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*
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*
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* Copyright 2021 RichardG.
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* Copyright 2021-2022 RichardG.
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdint.h>
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@@ -37,7 +37,10 @@
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#include <86box/nvr.h>
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#include <86box/nvr.h>
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#define CRYSTAL_NOEEPROM 0x100
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enum {
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enum {
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CRYSTAL_CS4235 = 0xdd,
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CRYSTAL_CS4236B = 0xcb,
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CRYSTAL_CS4236B = 0xcb,
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CRYSTAL_CS4237B = 0xc8,
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CRYSTAL_CS4237B = 0xc8,
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CRYSTAL_CS4238B = 0xc9
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CRYSTAL_CS4238B = 0xc9
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@@ -69,7 +72,7 @@ static const uint8_t cs4236b_eeprom[] = {
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0x10, 0x03, /* DMA routing */
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0x10, 0x03, /* DMA routing */
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/* PnP resources */
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/* PnP resources */
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0x0e, 0x63, 0x42, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, /* CSC4236, dummy checksum (filled in by isapnp_add_card) */
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0x0e, 0x63, 0x42, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, /* CSC4236, dummy checksum (filled in by isapnp_add_card) */
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0x0a, 0x10, 0x01, /* PnP version 1.0, vendor version 0.1 */
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0x0a, 0x10, 0x01, /* PnP version 1.0, vendor version 0.1 */
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0x82, 0x0e, 0x00, 'C', 'r', 'y', 's', 't', 'a', 'l', ' ', 'C', 'o', 'd', 'e' ,'c', 0x00, /* ANSI identifier */
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0x82, 0x0e, 0x00, 'C', 'r', 'y', 's', 't', 'a', 'l', ' ', 'C', 'o', 'd', 'e' ,'c', 0x00, /* ANSI identifier */
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@@ -312,7 +315,8 @@ cs423x_write(uint16_t addr, uint8_t val, void *priv)
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break;
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break;
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case 6: /* RAM Access End */
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case 6: /* RAM Access End */
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if (!val) {
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/* TriGem Delhi-III BIOS writes undocumented value 0x40 instead of 0x00. */
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if ((val == 0x00) || (val == 0x40)) {
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dev->ram_dl = 0;
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dev->ram_dl = 0;
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/* Update PnP state and resource data. */
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/* Update PnP state and resource data. */
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@@ -356,6 +360,20 @@ cs423x_slam_write(uint16_t addr, uint8_t val, void *priv)
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break;
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break;
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case CRYSTAL_SLAM_INDEX:
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case CRYSTAL_SLAM_INDEX:
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/* Intercept the Activate Audio Device command. */
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if (val == 0x79) {
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/* Apply the last logical device's configuration. */
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if (dev->slam_config) {
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cs423x_pnp_config_changed(dev->slam_ld, dev->slam_config, dev);
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free(dev->slam_config);
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dev->slam_config = NULL;
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}
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/* Exit out of SLAM. */
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dev->slam_state = CRYSTAL_SLAM_NONE;
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break;
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}
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/* Write register index. */
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/* Write register index. */
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dev->slam_reg = val;
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dev->slam_reg = val;
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dev->slam_state = CRYSTAL_SLAM_BYTE1;
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dev->slam_state = CRYSTAL_SLAM_BYTE1;
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@@ -429,18 +447,6 @@ cs423x_slam_write(uint16_t addr, uint8_t val, void *priv)
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/* Activate or deactivate the device. */
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/* Activate or deactivate the device. */
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dev->slam_config->activate = val & 0x01;
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dev->slam_config->activate = val & 0x01;
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break;
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break;
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case 0x79: /* activate chip */
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/* Apply the last logical device's configuration. */
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if (dev->slam_config) {
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cs423x_pnp_config_changed(dev->slam_ld, dev->slam_config, dev);
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free(dev->slam_config);
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dev->slam_config = NULL;
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}
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/* Exit out of SLAM. */
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dev->slam_state = CRYSTAL_SLAM_NONE;
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break;
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}
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}
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/* Prepare for the next register, unless a two-byte read returns above. */
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/* Prepare for the next register, unless a two-byte read returns above. */
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@@ -560,10 +566,12 @@ cs423x_pnp_enable(cs423x_t *dev, uint8_t update_rom, uint8_t update_hwconfig)
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}
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}
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/* Update SPS. */
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/* Update SPS. */
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if (dev->ram_data[0x4003] & 0x04)
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if (dev->type != CRYSTAL_CS4235) {
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dev->indirect_regs[8] |= 0x04;
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if (dev->ram_data[0x4003] & 0x04)
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else
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dev->indirect_regs[8] |= 0x04;
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dev->indirect_regs[8] &= ~0x04;
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else
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dev->indirect_regs[8] &= ~0x04;
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}
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/* Update IFM. */
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/* Update IFM. */
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if (dev->ram_data[0x4003] & 0x80)
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if (dev->ram_data[0x4003] & 0x80)
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@@ -723,8 +731,9 @@ cs423x_init(const device_t *info)
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memset(dev, 0, sizeof(cs423x_t));
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memset(dev, 0, sizeof(cs423x_t));
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/* Initialize model-specific data. */
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/* Initialize model-specific data. */
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dev->type = info->local;
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dev->type = info->local & 0xff;
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switch (dev->type) {
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switch (dev->type) {
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case CRYSTAL_CS4235:
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case CRYSTAL_CS4236B:
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case CRYSTAL_CS4236B:
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case CRYSTAL_CS4237B:
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case CRYSTAL_CS4237B:
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case CRYSTAL_CS4238B:
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case CRYSTAL_CS4238B:
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@@ -735,36 +744,45 @@ cs423x_init(const device_t *info)
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/* Different Chip Version and ID registers, which shouldn't be reset by ad1848_init */
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/* Different Chip Version and ID registers, which shouldn't be reset by ad1848_init */
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dev->ad1848.xregs[25] = dev->type;
|
dev->ad1848.xregs[25] = dev->type;
|
||||||
|
|
||||||
/* Load EEPROM contents from template. */
|
if (!(info->local & CRYSTAL_NOEEPROM)) {
|
||||||
memcpy(dev->eeprom_data, cs4236b_eeprom, sizeof(cs4236b_eeprom));
|
/* Load EEPROM contents from template. */
|
||||||
|
memcpy(dev->eeprom_data, cs4236b_eeprom, sizeof(cs4236b_eeprom));
|
||||||
|
|
||||||
/* Set content size. */
|
/* Set content size. */
|
||||||
dev->eeprom_data[2] = sizeof(cs4236b_eeprom) >> 8;
|
dev->eeprom_data[2] = sizeof(cs4236b_eeprom) >> 8;
|
||||||
dev->eeprom_data[3] = sizeof(cs4236b_eeprom) & 0xff;
|
dev->eeprom_data[3] = sizeof(cs4236b_eeprom) & 0xff;
|
||||||
|
|
||||||
/* Set PnP card ID and EEPROM file name. */
|
/* Set PnP card ID and EEPROM file name. */
|
||||||
switch (dev->type) {
|
switch (dev->type) {
|
||||||
case CRYSTAL_CS4236B:
|
case CRYSTAL_CS4235:
|
||||||
dev->nvr_path = "cs4236b.nvr";
|
dev->eeprom_data[8] = 0x05;
|
||||||
break;
|
dev->eeprom_data[16] = 0x08;
|
||||||
|
dev->eeprom_data[26] = 0x25;
|
||||||
|
dev->nvr_path = "cs4235.nvr";
|
||||||
|
break;
|
||||||
|
|
||||||
case CRYSTAL_CS4237B:
|
case CRYSTAL_CS4236B:
|
||||||
dev->eeprom_data[26] = 0x37;
|
dev->nvr_path = "cs4236b.nvr";
|
||||||
dev->nvr_path = "cs4237b.nvr";
|
break;
|
||||||
break;
|
|
||||||
|
|
||||||
case CRYSTAL_CS4238B:
|
case CRYSTAL_CS4237B:
|
||||||
dev->eeprom_data[26] = 0x38;
|
dev->eeprom_data[26] = 0x37;
|
||||||
dev->nvr_path = "cs4238b.nvr";
|
dev->nvr_path = "cs4237b.nvr";
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case CRYSTAL_CS4238B:
|
||||||
|
dev->eeprom_data[26] = 0x38;
|
||||||
|
dev->nvr_path = "cs4238b.nvr";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Load EEPROM contents from file if present. */
|
||||||
|
cs423x_nvram(dev, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Load EEPROM contents from file if present. */
|
|
||||||
cs423x_nvram(dev, 0);
|
|
||||||
|
|
||||||
/* Initialize game port. The '7B and '8B game port only responds to 6 I/O ports; the remaining
|
/* Initialize game port. The '7B and '8B game port only responds to 6 I/O ports; the remaining
|
||||||
2 ports are reserved on those chips, and probably connected to the Digital Assist feature. */
|
2 ports are reserved on those chips, and probably connected to the Digital Assist feature. */
|
||||||
dev->gameport = gameport_add((dev->type == CRYSTAL_CS4236B) ? &gameport_pnp_device : &gameport_pnp_6io_device);
|
dev->gameport = gameport_add(((dev->type == CRYSTAL_CS4235) || (dev->type == CRYSTAL_CS4236B)) ? &gameport_pnp_device : &gameport_pnp_6io_device);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@@ -787,6 +805,11 @@ cs423x_init(const device_t *info)
|
|||||||
cs423x_reset(dev);
|
cs423x_reset(dev);
|
||||||
sound_add_handler(cs423x_get_buffer, dev);
|
sound_add_handler(cs423x_get_buffer, dev);
|
||||||
|
|
||||||
|
/* Add Control/RAM backdoor handlers for CS4235. */
|
||||||
|
dev->ad1848.cram_priv = dev;
|
||||||
|
dev->ad1848.cram_read = cs423x_read;
|
||||||
|
dev->ad1848.cram_write = cs423x_write;
|
||||||
|
|
||||||
return dev;
|
return dev;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -817,6 +840,32 @@ cs423x_speed_changed(void *priv)
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
const device_t cs4235_device =
|
||||||
|
{
|
||||||
|
"Crystal CS4235",
|
||||||
|
"cs4235",
|
||||||
|
DEVICE_ISA | DEVICE_AT,
|
||||||
|
CRYSTAL_CS4235,
|
||||||
|
cs423x_init, cs423x_close, cs423x_reset,
|
||||||
|
{ NULL },
|
||||||
|
cs423x_speed_changed,
|
||||||
|
NULL,
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
|
const device_t cs4235_onboard_device =
|
||||||
|
{
|
||||||
|
"Crystal CS4235 (On-Board)",
|
||||||
|
"cs4235_onboard",
|
||||||
|
DEVICE_ISA | DEVICE_AT,
|
||||||
|
CRYSTAL_CS4235 | CRYSTAL_NOEEPROM,
|
||||||
|
cs423x_init, cs423x_close, cs423x_reset,
|
||||||
|
{ NULL },
|
||||||
|
cs423x_speed_changed,
|
||||||
|
NULL,
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
const device_t cs4236b_device =
|
const device_t cs4236b_device =
|
||||||
{
|
{
|
||||||
"Crystal CS4236B",
|
"Crystal CS4236B",
|
||||||
|
|||||||
@@ -106,6 +106,7 @@ static const SOUND_CARD sound_cards[] =
|
|||||||
{ &adgold_device },
|
{ &adgold_device },
|
||||||
{ &azt2316a_device },
|
{ &azt2316a_device },
|
||||||
{ &azt1605_device },
|
{ &azt1605_device },
|
||||||
|
{ &cs4235_device },
|
||||||
{ &cs4236b_device },
|
{ &cs4236b_device },
|
||||||
{ &sb_1_device },
|
{ &sb_1_device },
|
||||||
{ &sb_15_device },
|
{ &sb_15_device },
|
||||||
|
|||||||
Reference in New Issue
Block a user