Applied both mainline PCem commits;
Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
This commit is contained in:
OBattler
@@ -1,22 +1,20 @@
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#define OP_ARITH(name, operation, setflags, flagops, gettempc) \
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static int op ## name ## _b_rmw_a16(uint32_t fetchdat) \
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{ \
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uint8_t dst; \
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uint8_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = getr8(rm); \
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src = getr8(reg); \
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uint8_t dst = getr8(cpu_rm); \
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uint8_t src = getr8(cpu_reg); \
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setflags ## 8 flagops; \
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setr8(rm, operation); \
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setr8(cpu_rm, operation); \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteab(); if (abrt) return 1; \
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src = getr8(reg); \
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uint8_t dst = geteab(); if (abrt) return 1; \
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uint8_t src = getr8(cpu_reg); \
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seteab(operation); if (abrt) return 1; \
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setflags ## 8 flagops; \
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CLOCK_CYCLES(timing_mr); \
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@@ -25,22 +23,20 @@
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} \
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static int op ## name ## _b_rmw_a32(uint32_t fetchdat) \
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{ \
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uint8_t dst; \
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uint8_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = getr8(rm); \
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src = getr8(reg); \
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uint8_t dst = getr8(cpu_rm); \
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uint8_t src = getr8(cpu_reg); \
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setflags ## 8 flagops; \
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setr8(rm, operation); \
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setr8(cpu_rm, operation); \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteab(); if (abrt) return 1; \
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src = getr8(reg); \
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uint8_t dst = geteab(); if (abrt) return 1; \
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uint8_t src = getr8(cpu_reg); \
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seteab(operation); if (abrt) return 1; \
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setflags ## 8 flagops; \
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CLOCK_CYCLES(timing_mr); \
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@@ -50,22 +46,20 @@
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\
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static int op ## name ## _w_rmw_a16(uint32_t fetchdat) \
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{ \
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uint16_t dst; \
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uint16_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = cpu_state.regs[rm].w; \
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src = cpu_state.regs[reg].w; \
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uint16_t dst = cpu_state.regs[cpu_rm].w; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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setflags ## 16 flagops; \
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cpu_state.regs[rm].w = operation; \
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cpu_state.regs[cpu_rm].w = operation; \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteaw(); if (abrt) return 1; \
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src = cpu_state.regs[reg].w; \
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uint16_t dst = geteaw(); if (abrt) return 1; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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seteaw(operation); if (abrt) return 1; \
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setflags ## 16 flagops; \
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CLOCK_CYCLES(timing_mr); \
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@@ -74,22 +68,20 @@
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} \
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static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
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{ \
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uint16_t dst; \
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uint16_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = cpu_state.regs[rm].w; \
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src = cpu_state.regs[reg].w; \
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uint16_t dst = cpu_state.regs[cpu_rm].w; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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setflags ## 16 flagops; \
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cpu_state.regs[rm].w = operation; \
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cpu_state.regs[cpu_rm].w = operation; \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteaw(); if (abrt) return 1; \
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src = cpu_state.regs[reg].w; \
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uint16_t dst = geteaw(); if (abrt) return 1; \
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uint16_t src = cpu_state.regs[cpu_reg].w; \
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seteaw(operation); if (abrt) return 1; \
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setflags ## 16 flagops; \
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CLOCK_CYCLES(timing_mr); \
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@@ -99,22 +91,20 @@
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\
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static int op ## name ## _l_rmw_a16(uint32_t fetchdat) \
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{ \
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uint32_t dst; \
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uint32_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = cpu_state.regs[rm].l; \
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src = cpu_state.regs[reg].l; \
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uint32_t dst = cpu_state.regs[cpu_rm].l; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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setflags ## 32 flagops; \
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cpu_state.regs[rm].l = operation; \
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cpu_state.regs[cpu_rm].l = operation; \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteal(); if (abrt) return 1; \
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src = cpu_state.regs[reg].l; \
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uint32_t dst = geteal(); if (abrt) return 1; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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seteal(operation); if (abrt) return 1; \
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setflags ## 32 flagops; \
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CLOCK_CYCLES(timing_mrl); \
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@@ -123,22 +113,20 @@
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} \
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static int op ## name ## _l_rmw_a32(uint32_t fetchdat) \
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{ \
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uint32_t dst; \
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uint32_t src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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if (mod == 3) \
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if (cpu_mod == 3) \
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{ \
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dst = cpu_state.regs[rm].l; \
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src = cpu_state.regs[reg].l; \
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uint32_t dst = cpu_state.regs[cpu_rm].l; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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setflags ## 32 flagops; \
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cpu_state.regs[rm].l = operation; \
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cpu_state.regs[cpu_rm].l = operation; \
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CLOCK_CYCLES(timing_rr); \
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} \
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else \
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{ \
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dst = geteal(); if (abrt) return 1; \
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src = cpu_state.regs[reg].l; \
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uint32_t dst = geteal(); if (abrt) return 1; \
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uint32_t src = cpu_state.regs[cpu_reg].l; \
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seteal(operation); if (abrt) return 1; \
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setflags ## 32 flagops; \
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CLOCK_CYCLES(timing_mrl); \
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@@ -151,11 +139,11 @@
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uint8_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = getr8(reg); \
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dst = getr8(cpu_reg); \
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src = geteab(); if (abrt) return 1; \
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setflags ## 8 flagops; \
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setr8(reg, operation); \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
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setr8(cpu_reg, operation); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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return 0; \
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} \
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static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
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@@ -163,11 +151,11 @@
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uint8_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = getr8(reg); \
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dst = getr8(cpu_reg); \
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src = geteab(); if (abrt) return 1; \
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setflags ## 8 flagops; \
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setr8(reg, operation); \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
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setr8(cpu_reg, operation); \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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return 0; \
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} \
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\
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@@ -176,11 +164,11 @@
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uint16_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = cpu_state.regs[reg].w; \
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dst = cpu_state.regs[cpu_reg].w; \
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src = geteaw(); if (abrt) return 1; \
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setflags ## 16 flagops; \
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cpu_state.regs[reg].w = operation; \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
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cpu_state.regs[cpu_reg].w = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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return 0; \
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} \
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static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
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@@ -188,11 +176,11 @@
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uint16_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = cpu_state.regs[reg].w; \
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dst = cpu_state.regs[cpu_reg].w; \
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src = geteaw(); if (abrt) return 1; \
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setflags ## 16 flagops; \
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cpu_state.regs[reg].w = operation; \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm); \
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cpu_state.regs[cpu_reg].w = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
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return 0; \
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} \
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\
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@@ -201,11 +189,11 @@
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uint32_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_16(fetchdat); \
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dst = cpu_state.regs[reg].l; \
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dst = cpu_state.regs[cpu_reg].l; \
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src = geteal(); if (abrt) return 1; \
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setflags ## 32 flagops; \
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cpu_state.regs[reg].l = operation; \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
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cpu_state.regs[cpu_reg].l = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
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return 0; \
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} \
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static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
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@@ -213,11 +201,11 @@
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uint32_t dst, src; \
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if (gettempc) tempc = CF_SET() ? 1 : 0; \
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fetch_ea_32(fetchdat); \
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dst = cpu_state.regs[reg].l; \
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dst = cpu_state.regs[cpu_reg].l; \
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src = geteal(); if (abrt) return 1; \
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setflags ## 32 flagops; \
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cpu_state.regs[reg].l = operation; \
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml); \
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cpu_state.regs[cpu_reg].l = operation; \
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
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return 0; \
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} \
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\
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@@ -267,9 +255,9 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
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uint8_t dst;
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fetch_ea_16(fetchdat);
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dst = geteab(); if (abrt) return 1;
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setsub8(dst, getr8(reg));
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub8(dst, getr8(cpu_reg));
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_b_rmw_a32(uint32_t fetchdat)
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@@ -277,9 +265,9 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
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uint8_t dst;
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fetch_ea_32(fetchdat);
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dst = geteab(); if (abrt) return 1;
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setsub8(dst, getr8(reg));
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub8(dst, getr8(cpu_reg));
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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@@ -288,9 +276,9 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
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uint16_t dst;
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fetch_ea_16(fetchdat);
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dst = geteaw(); if (abrt) return 1;
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setsub16(dst, cpu_state.regs[reg].w);
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub16(dst, cpu_state.regs[cpu_reg].w);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_w_rmw_a32(uint32_t fetchdat)
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@@ -298,9 +286,9 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
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uint16_t dst;
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fetch_ea_32(fetchdat);
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dst = geteaw(); if (abrt) return 1;
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setsub16(dst, cpu_state.regs[reg].w);
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub16(dst, cpu_state.regs[cpu_reg].w);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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@@ -309,9 +297,9 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
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uint32_t dst;
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fetch_ea_16(fetchdat);
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dst = geteal(); if (abrt) return 1;
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setsub32(dst, cpu_state.regs[reg].l);
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub32(dst, cpu_state.regs[cpu_reg].l);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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static int opCMP_l_rmw_a32(uint32_t fetchdat)
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@@ -319,9 +307,9 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
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uint32_t dst;
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fetch_ea_32(fetchdat);
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dst = geteal(); if (abrt) return 1;
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setsub32(dst, cpu_state.regs[reg].l);
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if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((mod == 3) ? 2 : 5);
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setsub32(dst, cpu_state.regs[cpu_reg].l);
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if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
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else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
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return 0;
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}
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@@ -330,8 +318,8 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
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uint8_t src;
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fetch_ea_16(fetchdat);
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src = geteab(); if (abrt) return 1;
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setsub8(getr8(reg), src);
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
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setsub8(getr8(cpu_reg), src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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}
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static int opCMP_b_rm_a32(uint32_t fetchdat)
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@@ -339,8 +327,8 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
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uint8_t src;
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fetch_ea_32(fetchdat);
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src = geteab(); if (abrt) return 1;
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setsub8(getr8(reg), src);
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
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setsub8(getr8(cpu_reg), src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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}
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@@ -349,8 +337,8 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
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uint16_t src;
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fetch_ea_16(fetchdat);
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src = geteaw(); if (abrt) return 1;
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setsub16(cpu_state.regs[reg].w, src);
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
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setsub16(cpu_state.regs[cpu_reg].w, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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}
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static int opCMP_w_rm_a32(uint32_t fetchdat)
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@@ -358,8 +346,8 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
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uint16_t src;
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fetch_ea_32(fetchdat);
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src = geteaw(); if (abrt) return 1;
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setsub16(cpu_state.regs[reg].w, src);
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CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rm);
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setsub16(cpu_state.regs[cpu_reg].w, src);
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CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
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return 0;
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}
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|
||||
@@ -368,8 +356,8 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
|
||||
uint32_t src;
|
||||
fetch_ea_16(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(cpu_state.regs[reg].l, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
static int opCMP_l_rm_a32(uint32_t fetchdat)
|
||||
@@ -377,8 +365,8 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
|
||||
uint32_t src;
|
||||
fetch_ea_32(fetchdat);
|
||||
src = geteal(); if (abrt) return 1;
|
||||
setsub32(cpu_state.regs[reg].l, src);
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_rml);
|
||||
setsub32(cpu_state.regs[cpu_reg].l, src);
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -411,10 +399,10 @@ static int opTEST_b_a16(uint32_t fetchdat)
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_b_a32(uint32_t fetchdat)
|
||||
@@ -422,10 +410,10 @@ static int opTEST_b_a32(uint32_t fetchdat)
|
||||
uint8_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
temp2 = getr8(reg);
|
||||
temp2 = getr8(cpu_reg);
|
||||
setznp8(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -434,10 +422,10 @@ static int opTEST_w_a16(uint32_t fetchdat)
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].w;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_w_a32(uint32_t fetchdat)
|
||||
@@ -445,10 +433,10 @@ static int opTEST_w_a32(uint32_t fetchdat)
|
||||
uint16_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].w;
|
||||
temp2 = cpu_state.regs[cpu_reg].w;
|
||||
setznp16(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -457,10 +445,10 @@ static int opTEST_l_a16(uint32_t fetchdat)
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].l;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
static int opTEST_l_a32(uint32_t fetchdat)
|
||||
@@ -468,10 +456,10 @@ static int opTEST_l_a32(uint32_t fetchdat)
|
||||
uint32_t temp, temp2;
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
temp2 = cpu_state.regs[reg].l;
|
||||
temp2 = cpu_state.regs[cpu_reg].l;
|
||||
setznp32(temp & temp2);
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 5);
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -505,47 +493,47 @@ static int opTEST_EAX(uint32_t fetchdat)
|
||||
case 0x00: /*ADD ea, #*/ \
|
||||
setea ## ea_width(dst + src); if (abrt) return 1; \
|
||||
setadd ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x08: /*OR ea, #*/ \
|
||||
dst |= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x10: /*ADC ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst + src + tempc); if (abrt) return 1; \
|
||||
setadc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x18: /*SBB ea, #*/ \
|
||||
tempc = CF_SET() ? 1 : 0; \
|
||||
setea ## ea_width(dst - (src + tempc)); if (abrt) return 1; \
|
||||
setsbc ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x20: /*AND ea, #*/ \
|
||||
dst &= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x28: /*SUB ea, #*/ \
|
||||
setea ## ea_width(dst - src); if (abrt) return 1; \
|
||||
setsub ## flag_width(dst, src); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x30: /*XOR ea, #*/ \
|
||||
dst ^= src; \
|
||||
setea ## ea_width(dst); if (abrt) return 1; \
|
||||
setznp ## flag_width(dst); \
|
||||
CLOCK_CYCLES((mod == 3) ? timing_rr : timing_mr); \
|
||||
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
|
||||
break; \
|
||||
case 0x38: /*CMP ea, #*/ \
|
||||
setsub ## flag_width(dst, src); \
|
||||
if (is486) CLOCK_CYCLES((mod == 3) ? 1 : 2); \
|
||||
else CLOCK_CYCLES((mod == 3) ? 2 : 7); \
|
||||
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
|
||||
break; \
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user