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Applied both mainline PCem commits;

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Fixed the RTL8029AS again (one of my "fixes" broke it);
RTL8029AS PCI register 4 is now written to;
Added incomplete (and currently commented out) emulation of the AWE64 PCI;
Replaced sector-based floppy emulation with more accurate code.
This commit is contained in:
OBattler
2016-08-15 01:34:46 +02:00
parent 2cf962445f
commit 1433d9a073
53 changed files with 2335 additions and 1828 deletions
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68
src/x86_ops_mov_ctrl.h
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@@ -7,27 +7,27 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
switch (reg)
switch (cpu_reg)
{
case 0:
cpu_state.regs[rm].l = cr0;
cpu_state.regs[cpu_rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
cpu_state.regs[rm].l = cr2;
cpu_state.regs[cpu_rm].l = cr2;
break;
case 3:
cpu_state.regs[rm].l = cr3;
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
cpu_state.regs[rm].l = cr4;
cpu_state.regs[cpu_rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
cpu_state.pc = oldpc;
x86illegal();
break;
@@ -44,27 +44,27 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
switch (reg)
switch (cpu_reg)
{
case 0:
cpu_state.regs[rm].l = cr0;
cpu_state.regs[cpu_rm].l = cr0;
if (is486)
cpu_state.regs[rm].l |= 0x10; /*ET hardwired on 486*/
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:
cpu_state.regs[rm].l = cr2;
cpu_state.regs[cpu_rm].l = cr2;
break;
case 3:
cpu_state.regs[rm].l = cr3;
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_hasCR4)
{
cpu_state.regs[rm].l = cr4;
cpu_state.regs[cpu_rm].l = cr4;
break;
}
default:
pclog("Bad read of CR%i %i\n",rmdat&7,reg);
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
cpu_state.pc = oldpc;
x86illegal();
break;
@@ -82,7 +82,7 @@ static int opMOV_r_DRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
cpu_state.regs[rm].l = dr[reg];
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
return 0;
}
@@ -95,7 +95,7 @@ static int opMOV_r_DRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
cpu_state.regs[rm].l = dr[reg];
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
CLOCK_CYCLES(6);
return 0;
}
@@ -109,33 +109,33 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
switch (reg)
switch (cpu_reg)
{
case 0:
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = cpu_state.regs[rm].l;
cr2 = cpu_state.regs[cpu_rm].l;
break;
case 3:
cr3 = cpu_state.regs[rm].l;
cr3 = cpu_state.regs[cpu_rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pclog("Bad load CR%i\n", cpu_reg);
cpu_state.pc = oldpc;
x86illegal();
break;
@@ -152,33 +152,33 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
switch (reg)
switch (cpu_reg)
{
case 0:
if ((cpu_state.regs[rm].l ^ cr0) & 0x80000001)
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
flushmmucache();
cr0 = cpu_state.regs[rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
cr2 = cpu_state.regs[rm].l;
cr2 = cpu_state.regs[cpu_rm].l;
break;
case 3:
cr3 = cpu_state.regs[rm].l;
cr3 = cpu_state.regs[cpu_rm].l;
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
cr4 = cpu_state.regs[rm].l & cpu_CR4_mask;
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;
}
default:
pclog("Bad load CR%i\n", reg);
pclog("Bad load CR%i\n", cpu_reg);
cpu_state.pc = oldpc;
x86illegal();
break;
@@ -196,7 +196,7 @@ static int opMOV_DRx_r_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = cpu_state.regs[rm].l;
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
return 0;
}
@@ -209,7 +209,7 @@ static int opMOV_DRx_r_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
dr[reg] = cpu_state.regs[rm].l;
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
CLOCK_CYCLES(6);
return 0;
}
@@ -223,7 +223,7 @@ static int opMOV_r_TRx_a16(uint32_t fetchdat)
return 1;
}
fetch_ea_16(fetchdat);
cpu_state.regs[rm].l = 0;
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}
@@ -236,7 +236,7 @@ static int opMOV_r_TRx_a32(uint32_t fetchdat)
return 1;
}
fetch_ea_32(fetchdat);
cpu_state.regs[rm].l = 0;
cpu_state.regs[cpu_rm].l = 0;
CLOCK_CYCLES(6);
return 0;
}