claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Applied both mainline PCem commits;

Browse Source 
Fixed the RTL8029AS again (one of my "fixes" broke it);
RTL8029AS PCI register 4 is now written to;
Added incomplete (and currently commented out) emulation of the AWE64 PCI;
Replaced sector-based floppy emulation with more accurate code.
This commit is contained in:
OBattler
2016-08-15 01:34:46 +02:00
parent 2cf962445f
commit 1433d9a073
53 changed files with 2335 additions and 1828 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/x86_ops_xchg.h
View File

@@ -3,9 +3,9 @@ static int opXCHG_b_a16(uint32_t fetchdat)
uint8_t temp;
fetch_ea_16(fetchdat);
temp = geteab(); if (abrt) return 1;
seteab(getr8(reg)); if (abrt) return 1;
setr8(reg, temp);
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteab(getr8(cpu_reg)); if (abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}
static int opXCHG_b_a32(uint32_t fetchdat)
@@ -13,9 +13,9 @@ static int opXCHG_b_a32(uint32_t fetchdat)
uint8_t temp;
fetch_ea_32(fetchdat);
temp = geteab(); if (abrt) return 1;
seteab(getr8(reg)); if (abrt) return 1;
setr8(reg, temp);
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteab(getr8(cpu_reg)); if (abrt) return 1;
setr8(cpu_reg, temp);
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}
@@ -24,9 +24,9 @@ static int opXCHG_w_a16(uint32_t fetchdat)
uint16_t temp;
fetch_ea_16(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}
static int opXCHG_w_a32(uint32_t fetchdat)
@@ -34,9 +34,9 @@ static int opXCHG_w_a32(uint32_t fetchdat)
uint16_t temp;
fetch_ea_32(fetchdat);
temp = geteaw(); if (abrt) return 1;
seteaw(cpu_state.regs[reg].w); if (abrt) return 1;
cpu_state.regs[reg].w = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteaw(cpu_state.regs[cpu_reg].w); if (abrt) return 1;
cpu_state.regs[cpu_reg].w = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}
@@ -45,9 +45,9 @@ static int opXCHG_l_a16(uint32_t fetchdat)
uint32_t temp;
fetch_ea_16(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}
static int opXCHG_l_a32(uint32_t fetchdat)
@@ -55,9 +55,9 @@ static int opXCHG_l_a32(uint32_t fetchdat)
uint32_t temp;
fetch_ea_32(fetchdat);
temp = geteal(); if (abrt) return 1;
seteal(cpu_state.regs[reg].l); if (abrt) return 1;
cpu_state.regs[reg].l = temp;
CLOCK_CYCLES((mod == 3) ? 3 : 5);
seteal(cpu_state.regs[cpu_reg].l); if (abrt) return 1;
cpu_state.regs[cpu_reg].l = temp;
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 5);
return 0;
}