Added PAE, ported K6, P6, and WinChip 2 timings to the old recompiler, added a bunch of CPU's to the old recompiler, done some x87 fixes for both recompilers, added PAE, and fixed root directory entries for single-sided 5.25" DD floppies in the New Floppy Image dialog.
This commit is contained in:
OBattler
@@ -13,180 +13,33 @@
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* Author: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2016-2018 Miran Grca.
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*/
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/* 0 = Limit 0-15
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1 = Base 0-15
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2 = Base 16-23 (bits 0-7), Access rights
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8-11 Type
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12 S
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13, 14 DPL
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15 P
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3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
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4 A
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6 DB
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7 G */
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#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
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#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
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#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
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/* 0F 05 */
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static int opSYSCALL(uint32_t fetchdat)
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static int
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opSYSCALL(uint32_t fetchdat)
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{
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uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
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uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
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if (!(cr0 & 1)) return internal_illegal("SYSCALL: CPU not in protected mode");
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if (!AMD_SYSCALL_SB) return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
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/* Set VM, IF, RF to 0. */
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/* cpu_state.eflags &= ~0x00030200;
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cpu_state.flags &= ~0x0200; */
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/* Let's do this by the AMD spec. */
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ECX = cpu_state.pc;
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cpu_state.eflags &= ~0x0002;
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cpu_state.flags &= ~0x0200;
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/* CS */
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cpu_state.seg_cs.seg = AMD_SYSCALL_SB & ~7;
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if (AMD_SYSCALL_SB & 4)
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{
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if (cpu_state.seg_cs.seg >= ldt.limit)
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{
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x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSCALL_SB,ldt.limit);
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x86gpf(NULL, AMD_SYSCALL_SB & ~3);
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return 1;
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}
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cpu_state.seg_cs.seg +=ldt.base;
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}
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else
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{
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if (cpu_state.seg_cs.seg >= gdt.limit)
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{
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x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSCALL_SB,gdt.limit);
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x86gpf(NULL, AMD_SYSCALL_SB & ~3);
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return 1;
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}
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cpu_state.seg_cs.seg += gdt.base;
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}
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cpl_override = 1;
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syscall_cs_seg_data[0] = 0xFFFF;
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syscall_cs_seg_data[1] = 0;
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syscall_cs_seg_data[2] = 0x9B00;
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syscall_cs_seg_data[3] = 0xC0;
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cpl_override = 0;
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use32 = 0x300;
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CS = (AMD_SYSCALL_SB & ~3) | 0;
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do_seg_load(&cpu_state.seg_cs, syscall_cs_seg_data);
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use32 = 0x300;
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CS = (CS & 0xFFFC) | 0;
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cpu_state.seg_cs.limit = 0xFFFFFFFF;
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cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
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/* SS */
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syscall_ss_seg_data[0] = 0xFFFF;
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syscall_ss_seg_data[1] = 0;
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syscall_ss_seg_data[2] = 0x9300;
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syscall_ss_seg_data[3] = 0xC0;
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do_seg_load(&cpu_state.seg_ss, syscall_ss_seg_data);
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cpu_state.seg_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
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stack32 = 1;
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cpu_state.seg_ss.limit = 0xFFFFFFFF;
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cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
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cpu_state.seg_ss.checked = 0;
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cpu_state.pc = AMD_SYSCALL_EIP;
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int ret = syscall(fetchdat);
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if (ret <= 1) {
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
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PREFETCH_FLUSH();
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CPU_BLOCK_END();
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}
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return 0;
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return ret;
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}
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/* 0F 07 */
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static int opSYSRET(uint32_t fetchdat)
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static int
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opSYSRET(uint32_t fetchdat)
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{
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uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
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uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
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if (!AMD_SYSRET_SB) return internal_illegal("SYSRET: CS MSR is zero");
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if (!(cr0 & 1)) return internal_illegal("SYSRET: CPU not in protected mode");
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cpu_state.pc = ECX;
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cpu_state.eflags |= (1 << 1);
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/* CS */
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cpu_state.seg_cs.seg = AMD_SYSRET_SB & ~7;
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if (AMD_SYSRET_SB & 4)
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{
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if (cpu_state.seg_cs.seg >= ldt.limit)
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{
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x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSRET_SB,ldt.limit);
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x86gpf(NULL, AMD_SYSRET_SB & ~3);
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return 1;
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}
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cpu_state.seg_cs.seg +=ldt.base;
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}
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else
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{
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if (cpu_state.seg_cs.seg >= gdt.limit)
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{
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x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSRET_SB,gdt.limit);
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x86gpf(NULL, AMD_SYSRET_SB & ~3);
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return 1;
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}
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cpu_state.seg_cs.seg += gdt.base;
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}
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cpl_override = 1;
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sysret_cs_seg_data[0] = 0xFFFF;
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sysret_cs_seg_data[1] = 0;
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sysret_cs_seg_data[2] = 0xFB00;
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sysret_cs_seg_data[3] = 0xC0;
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cpl_override = 0;
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use32 = 0x300;
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CS = (AMD_SYSRET_SB & ~3) | 3;
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do_seg_load(&cpu_state.seg_cs, sysret_cs_seg_data);
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flushmmucache_cr3();
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use32 = 0x300;
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CS = (CS & 0xFFFC) | 3;
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cpu_state.seg_cs.limit = 0xFFFFFFFF;
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cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
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/* SS */
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sysret_ss_seg_data[0] = 0xFFFF;
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sysret_ss_seg_data[1] = 0;
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sysret_ss_seg_data[2] = 0xF300;
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sysret_ss_seg_data[3] = 0xC0;
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do_seg_load(&cpu_state.seg_ss, sysret_ss_seg_data);
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cpu_state.seg_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
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stack32 = 1;
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cpu_state.seg_ss.limit = 0xFFFFFFFF;
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cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
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cpu_state.seg_ss.checked = 0;
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int ret = sysret(fetchdat);
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if (ret <= 1) {
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CLOCK_CYCLES(20);
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PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
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PREFETCH_FLUSH();
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CPU_BLOCK_END();
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}
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return 0;
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return ret;
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}
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