FDC: Fix DOR FINTR disabling, fixes #5851.
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@@ -335,14 +335,17 @@ fdc_int(fdc_t *fdc, int set_fintr)
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{
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{
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int ienable = 0;
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int ienable = 0;
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if (!(fdc->flags & FDC_FLAG_PCJR))
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if (fdc->flags & FDC_FLAG_PS2_MCA)
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ienable = 1;
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else if (!(fdc->flags & FDC_FLAG_PCJR))
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ienable = !!(fdc->dor & 8);
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ienable = !!(fdc->dor & 8);
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if (ienable)
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if (ienable) {
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picint(1 << fdc->irq);
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picint(1 << fdc->irq);
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if (set_fintr)
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if (set_fintr)
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fdc->fintr = 1;
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fdc->fintr = 1;
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}
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fdc_log("fdc_int(%i): fdc->fintr = %i\n", set_fintr, fdc->fintr);
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fdc_log("fdc_int(%i): fdc->fintr = %i\n", set_fintr, fdc->fintr);
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}
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}
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@@ -762,9 +765,17 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
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fdc->st0 &= ~0x07;
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fdc->st0 &= ~0x07;
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fdc->st0 |= (fdd_get_head(0) ? 4 : 0);
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fdc->st0 |= (fdd_get_head(0) ? 4 : 0);
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} else {
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} else {
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if (!(val & 8) && (fdc->dor & 8)) {
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/*
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fdc->tc = 1;
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Writing this bit to logic "1" will enable the DRQ,
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fdc_int(fdc, 1);
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nDACK, TC and FINTR outputs. This bit being a
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logic "0" will disable the nDACK and TC inputs, and
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hold the DRQ and FINTR outputs in a high
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impedance state.
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*/
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if (!(val & 8) && (fdc->dor & 8) && !(fdc->flags & FDC_FLAG_PS2_MCA)) {
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fdc->tc = 1;
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fdc->fintr = 0;
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picintc(1 << fdc->irq);
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}
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}
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if (!(val & 4)) {
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if (!(val & 4)) {
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fdd_stop(real_drive(fdc, val & 3));
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fdd_stop(real_drive(fdc, val & 3));
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