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C&T 69000: Rewrite the PCI register handling and intialize the registers to sane default, fixes the card's detection by the Windows 98 driver installer.

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This commit is contained in:
OBattler
2025-03-17 04:29:58 +01:00
parent 79134f3b21
commit 49463607c1
1 changed files with 144 additions and 104 deletions
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248
src/video/vid_chips_69000.c
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@@ -107,6 +107,7 @@ typedef struct chips_69000_t {
uint8_t mm_regs[256], mm_index; uint8_t mm_regs[256], mm_index;
uint8_t flat_panel_regs[256], flat_panel_index; uint8_t flat_panel_regs[256], flat_panel_index;
uint8_t ext_regs[256], ext_index; uint8_t ext_regs[256], ext_index;
uint8_t pci_regs[256];
union { union {
uint32_t mem_regs[4]; uint32_t mem_regs[4];
@@ -2156,57 +2157,74 @@ static uint8_t
chips_69000_pci_read(UNUSED(int func), int addr, void *priv) chips_69000_pci_read(UNUSED(int func), int addr, void *priv)
{ {
chips_69000_t *chips = (chips_69000_t *) priv; chips_69000_t *chips = (chips_69000_t *) priv;
uint8_t ret = 0x00;
{ switch (addr) {
switch (addr) { case 0x00:
case 0x00: ret = 0x2c;
return 0x2C; break;
case 0x01: case 0x01:
return 0x10; ret = 0x10;
case 0x02: break;
return 0xC0; case 0x02:
case 0x03: ret = 0xc0;
return 0x00; break;
case 0x04: case 0x03:
return (chips->pci_conf_status & 0b11100011) | 0x80; ret = 0x00;
case 0x06: break;
return 0x80;
case 0x07: case 0x04:
return 0x02; ret = (chips->pci_conf_status & 0x73) | 0x80;
case 0x08: break;
case 0x09: case 0x05:
case 0x0a: ret = chips->pci_regs[addr] & 0x01;
return 0x00; break;
case 0x0b: case 0x06:
return 0x03; ret = 0x80;
case 0x13: break;
return chips->linear_mapping.base >> 24; case 0x07:
case 0x30: ret = chips->pci_regs[addr] | 0x02;
return chips->pci_rom_enable & 0x1; break;
case 0x31:
return 0x0; case 0x0b:
case 0x32: ret = 0x03;
return chips->rom_addr & 0xFF; break;
case 0x33:
return (chips->rom_addr & 0xFF00) >> 8; case 0x13:
case 0x3c: ret = chips->linear_mapping.base >> 24;
return chips->pci_line_interrupt; break;
case 0x3d:
return 0x01; case 0x2c ... 0x2d:
case 0x2C: case 0x6c ... 0x6d:
case 0x2D: ret = chips->subsys_vid_b[addr & 1];
case 0x6C: break;
case 0x6D: case 0x2e ... 0x2f:
return (chips->subsys_vid >> ((addr & 1) * 8)) & 0xFF; case 0x6e ... 0x6f:
case 0x2E: ret = chips->subsys_pid_b[addr & 1];
case 0x2F: break;
case 0x6E:
case 0x6F: case 0x30:
return (chips->subsys_pid >> ((addr & 1) * 8)) & 0xFF; ret = chips->pci_rom_enable & 0x1;
default: break;
return 0x00; case 0x32:
} ret = chips->rom_addr & 0xff;
break;
case 0x33:
ret = (chips->rom_addr & 0xff00) >> 8;
break;
case 0x3c:
ret = chips->pci_line_interrupt;
break;
case 0x3d:
ret = 0x01;
break;
default:
break;
} }
return ret;
} }
static void static void
@@ -2214,67 +2232,77 @@ chips_69000_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{ {
chips_69000_t *chips = (chips_69000_t *) priv; chips_69000_t *chips = (chips_69000_t *) priv;
{ switch (addr) {
switch (addr) { case 0x04:
case 0x04: chips->pci_conf_status = val;
{ io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
chips->pci_conf_status = val; mem_mapping_disable(&chips->linear_mapping);
io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); mem_mapping_disable(&chips->svga.mapping);
mem_mapping_disable(&chips->linear_mapping); if (!chips->on_board)
mem_mapping_disable(&chips->svga.mapping); mem_mapping_disable(&chips->bios_rom.mapping);
if (chips->pci_conf_status & PCI_COMMAND_IO) { if (val & PCI_COMMAND_IO)
io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips); io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
} if (val & PCI_COMMAND_MEM) {
if (chips->pci_conf_status & PCI_COMMAND_MEM) { if (!chips->on_board && (chips->pci_rom_enable & 1))
mem_mapping_enable(&chips->svga.mapping); mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
if (chips->linear_mapping.base) mem_mapping_enable(&chips->svga.mapping);
mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); if (chips->linear_mapping.base > 0x00000000)
} mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24));
break; }
} break;
case 0x13: case 0x05:
{ chips->pci_regs[addr] = val & 0x01;
chips->linear_mapping.base = val << 24; break;
if (chips->linear_mapping.base) case 0x07:
mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24)); chips->pci_regs[addr] &= ~(val & 0xc8);
break; break;
}
case 0x3c: case 0x13:
chips->pci_line_interrupt = val; chips->linear_mapping.base = val << 24;
break; mem_mapping_disable(&chips->linear_mapping);
case 0x30: if ((chips->pci_conf_status & PCI_COMMAND_MEM) &&
if (chips->on_board) break; (chips->linear_mapping.base > 0x00000000))
mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24));
break;
case 0x30:
if (!chips->on_board) {
chips->pci_rom_enable = val & 0x1; chips->pci_rom_enable = val & 0x1;
mem_mapping_disable(&chips->bios_rom.mapping); mem_mapping_disable(&chips->bios_rom.mapping);
if (chips->pci_rom_enable & 1) { if ((chips->pci_conf_status & PCI_COMMAND_MEM) &&
(chips->pci_rom_enable & 1))
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
} }
break; break;
case 0x32: case 0x32:
if (chips->on_board) break; if (!chips->on_board) {
chips->rom_addr &= ~0xFF; chips->rom_addr &= ~0xff;
chips->rom_addr |= val & 0xFC; chips->rom_addr |= val & 0xfc;
if (chips->pci_rom_enable & 1) { if ((chips->pci_conf_status & PCI_COMMAND_MEM) &&
(chips->pci_rom_enable & 1))
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
} }
break; break;
case 0x33: case 0x33:
if (chips->on_board) break; if (!chips->on_board) {
chips->rom_addr &= ~0xFF00; chips->rom_addr &= ~0xff00;
chips->rom_addr |= (val << 8); chips->rom_addr |= (val << 8);
if (chips->pci_rom_enable & 1) { if ((chips->pci_conf_status & PCI_COMMAND_MEM) &&
(chips->pci_rom_enable & 1))
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000); mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
} }
break; break;
case 0x6C:
case 0x6D: case 0x3c:
chips->subsys_vid_b[addr & 1] = val; chips->pci_line_interrupt = val;
break; break;
case 0x6E:
case 0x6F: case 0x6c ... 0x6d:
chips->subsys_pid_b[addr & 1] = val; chips->subsys_vid_b[addr & 1] = val;
break; break;
} case 0x6e ... 0x6f:
chips->subsys_pid_b[addr & 1] = val;
break;
} }
} }
@@ -2839,6 +2867,18 @@ chips_69000_init(const device_t *info)
chips->flat_panel_regs[0x01] = 1; chips->flat_panel_regs[0x01] = 1;
chips->pci_conf_status = 0x00;
chips->pci_rom_enable = 0x00;
chips->rom_addr = 0x0000;
chips->subsys_vid = 0x102c;
chips->subsys_pid = 0x00c0;
io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
mem_mapping_disable(&chips->linear_mapping);
mem_mapping_disable(&chips->svga.mapping);
if (!chips->on_board)
mem_mapping_disable(&chips->bios_rom.mapping);
*reset_state = *chips; *reset_state = *chips;
return chips; return chips;