Merge pull request #5181 from 86Box/tc1995
More changes to the 5380 chips (January 26th, 2025)
This commit is contained in:
@@ -74,6 +74,7 @@ typedef struct ncr_t {
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uint8_t output_data;
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uint8_t tx_data;
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uint8_t irq_state;
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uint8_t isr_reg;
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uint8_t bus;
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@@ -195,7 +195,7 @@ ncr5380_write(uint16_t port, uint8_t val, ncr_t *ncr)
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break;
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case 5: /* start DMA Send */
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pclog("Write: start DMA send register\n");
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ncr5380_log("Write: start DMA send register\n");
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/*a Write 6/10 has occurred, start the timer when the block count is loaded*/
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scsi_bus->tx_mode = DMA_OUT_TX_BUS;
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if (ncr->dma_send_ext)
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@@ -238,7 +238,7 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
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} else
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ret = ncr->output_data;
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ncr5380_log("[%04X:%08X]: Data Bus Phase, ret=%02x, clearreq=%d, waitdata=%x, txmode=%x.\n", CS, cpu_state.pc, ret, scsi_bus->clear_req, scsi_bus->wait_data, scsi_bus->tx_mode);
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ncr5380_log("[%04X:%08X]: Data Bus Phase, CMDissued=%d, ret=%02x, clearreq=%d, waitdata=%x, txmode=%x.\n", CS, cpu_state.pc, scsi_bus->command_issued, ret, scsi_bus->clear_req, scsi_bus->wait_data, scsi_bus->tx_mode);
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} else {
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/*Return the data from the SCSI bus*/
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bus = scsi_bus_read(scsi_bus);
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@@ -271,10 +271,6 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
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ret |= BUS_SEL;
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if (ncr->icr & ICR_BSY)
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ret |= BUS_BSY;
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/*Note by TC1995: Horrible hack, I know.*/
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(void) scsi_bus_read(scsi_bus);
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(void) scsi_bus_read(scsi_bus);
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break;
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case 5: /* Bus and Status register */
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@@ -319,6 +315,7 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
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ret |= STATUS_BUSY_ERROR;
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}
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ret |= (ncr->isr & (STATUS_INT | STATUS_END_OF_DMA));
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ncr->isr_reg = ret;
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break;
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case 6:
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@@ -180,7 +180,10 @@ ncr53c400_write(uint32_t addr, uint8_t val, void *priv)
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}
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if ((ncr->mode & MODE_DMA) && (dev->buffer_length > 0)) {
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memset(ncr400->buffer, 0, MIN(128, dev->buffer_length));
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timer_on_auto(&ncr400->timer, scsi_bus->period);
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if (ncr400->type == ROM_T130B)
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timer_on_auto(&ncr400->timer, 10.0);
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else
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timer_on_auto(&ncr400->timer, scsi_bus->period);
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ncr53c400_log("DMA timer on=%02x, callback=%lf, scsi buflen=%d, waitdata=%d, waitcomplete=%d, clearreq=%d, p=%lf enabled=%d.\n",
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ncr->mode & MODE_MONITOR_BUSY, scsi_device_get_callback(dev), dev->buffer_length, scsi_bus->wait_data, scsi_bus->wait_complete, scsi_bus->clear_req, scsi_bus->period, timer_is_enabled(&ncr400->timer));
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} else
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@@ -391,17 +394,20 @@ t130b_in(uint16_t port, void *priv)
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}
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static void
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ncr53c400_dma_mode_ext(void *priv, UNUSED(void *ext_priv), uint8_t val)
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ncr53c400_dma_mode_ext(void *priv, void *ext_priv, uint8_t val)
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{
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ncr53c400_t *ncr400 = (ncr53c400_t *) ext_priv;
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ncr_t *ncr = (ncr_t *) priv;
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scsi_bus_t *scsi_bus = &ncr->scsibus;
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/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
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ncr53c400_log("NCR 53c400: BlockCountLoaded=%d, DMA mode enabled=%02x, valDMA=%02x.\n", ncr400->block_count_loaded, ncr->mode & MODE_DMA, val & MODE_DMA);
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if (!(val & MODE_DMA) && (ncr->mode & MODE_DMA)) {
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ncr->tcr &= ~TCR_LAST_BYTE_SENT;
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ncr->isr &= ~STATUS_END_OF_DMA;
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scsi_bus->tx_mode = PIO_TX_BUS;
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ncr53c400_log("NCR 53c400: Loaded?=%d, DMA mode enabled=%02x, valDMA=%02x.\n", ncr400->block_count_loaded, ncr->mode & MODE_DMA, val & MODE_DMA);
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if (!ncr400->block_count_loaded) {
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if (!(val & MODE_DMA)) {
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ncr->tcr &= ~TCR_LAST_BYTE_SENT;
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ncr->isr &= ~STATUS_END_OF_DMA;
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scsi_bus->tx_mode = PIO_TX_BUS;
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}
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}
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}
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@@ -417,8 +423,13 @@ ncr53c400_callback(void *priv)
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uint8_t temp;
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uint8_t status;
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if (scsi_bus->tx_mode != PIO_TX_BUS)
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timer_on_auto(&ncr400->timer, 1.0);
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if (scsi_bus->tx_mode != PIO_TX_BUS) {
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if (ncr400->type == ROM_T130B) {
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ncr53c400_log("PERIOD T130B DMA=%lf.\n", scsi_bus->period / 200.0);
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timer_on_auto(&ncr400->timer, scsi_bus->period / 200.0);
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} else
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timer_on_auto(&ncr400->timer, 1.0);
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}
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if (scsi_bus->data_wait & 1) {
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scsi_bus->clear_req = 3;
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@@ -727,7 +738,6 @@ ncr53c400_init(const device_t *info)
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scsi_bus->speed = 0.2;
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scsi_bus->divider = 2.0;
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scsi_bus->multi = 1.750;
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return ncr400;
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}
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