Merge pull request #5181 from 86Box/tc1995

More changes to the 5380 chips (January 26th, 2025)
This commit is contained in:
Miran Grča
2025-01-26 15:56:54 +01:00
committed by GitHub
3 changed files with 24 additions and 16 deletions

View File

@@ -74,6 +74,7 @@ typedef struct ncr_t {
uint8_t output_data;
uint8_t tx_data;
uint8_t irq_state;
uint8_t isr_reg;
uint8_t bus;

View File

@@ -195,7 +195,7 @@ ncr5380_write(uint16_t port, uint8_t val, ncr_t *ncr)
break;
case 5: /* start DMA Send */
pclog("Write: start DMA send register\n");
ncr5380_log("Write: start DMA send register\n");
/*a Write 6/10 has occurred, start the timer when the block count is loaded*/
scsi_bus->tx_mode = DMA_OUT_TX_BUS;
if (ncr->dma_send_ext)
@@ -238,7 +238,7 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
} else
ret = ncr->output_data;
ncr5380_log("[%04X:%08X]: Data Bus Phase, ret=%02x, clearreq=%d, waitdata=%x, txmode=%x.\n", CS, cpu_state.pc, ret, scsi_bus->clear_req, scsi_bus->wait_data, scsi_bus->tx_mode);
ncr5380_log("[%04X:%08X]: Data Bus Phase, CMDissued=%d, ret=%02x, clearreq=%d, waitdata=%x, txmode=%x.\n", CS, cpu_state.pc, scsi_bus->command_issued, ret, scsi_bus->clear_req, scsi_bus->wait_data, scsi_bus->tx_mode);
} else {
/*Return the data from the SCSI bus*/
bus = scsi_bus_read(scsi_bus);
@@ -271,10 +271,6 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
ret |= BUS_SEL;
if (ncr->icr & ICR_BSY)
ret |= BUS_BSY;
/*Note by TC1995: Horrible hack, I know.*/
(void) scsi_bus_read(scsi_bus);
(void) scsi_bus_read(scsi_bus);
break;
case 5: /* Bus and Status register */
@@ -319,6 +315,7 @@ ncr5380_read(uint16_t port, ncr_t *ncr)
ret |= STATUS_BUSY_ERROR;
}
ret |= (ncr->isr & (STATUS_INT | STATUS_END_OF_DMA));
ncr->isr_reg = ret;
break;
case 6:

View File

@@ -180,7 +180,10 @@ ncr53c400_write(uint32_t addr, uint8_t val, void *priv)
}
if ((ncr->mode & MODE_DMA) && (dev->buffer_length > 0)) {
memset(ncr400->buffer, 0, MIN(128, dev->buffer_length));
timer_on_auto(&ncr400->timer, scsi_bus->period);
if (ncr400->type == ROM_T130B)
timer_on_auto(&ncr400->timer, 10.0);
else
timer_on_auto(&ncr400->timer, scsi_bus->period);
ncr53c400_log("DMA timer on=%02x, callback=%lf, scsi buflen=%d, waitdata=%d, waitcomplete=%d, clearreq=%d, p=%lf enabled=%d.\n",
ncr->mode & MODE_MONITOR_BUSY, scsi_device_get_callback(dev), dev->buffer_length, scsi_bus->wait_data, scsi_bus->wait_complete, scsi_bus->clear_req, scsi_bus->period, timer_is_enabled(&ncr400->timer));
} else
@@ -391,17 +394,20 @@ t130b_in(uint16_t port, void *priv)
}
static void
ncr53c400_dma_mode_ext(void *priv, UNUSED(void *ext_priv), uint8_t val)
ncr53c400_dma_mode_ext(void *priv, void *ext_priv, uint8_t val)
{
ncr53c400_t *ncr400 = (ncr53c400_t *) ext_priv;
ncr_t *ncr = (ncr_t *) priv;
scsi_bus_t *scsi_bus = &ncr->scsibus;
/*When a pseudo-DMA transfer has completed (Send or Initiator Receive), mark it as complete and idle the status*/
ncr53c400_log("NCR 53c400: BlockCountLoaded=%d, DMA mode enabled=%02x, valDMA=%02x.\n", ncr400->block_count_loaded, ncr->mode & MODE_DMA, val & MODE_DMA);
if (!(val & MODE_DMA) && (ncr->mode & MODE_DMA)) {
ncr->tcr &= ~TCR_LAST_BYTE_SENT;
ncr->isr &= ~STATUS_END_OF_DMA;
scsi_bus->tx_mode = PIO_TX_BUS;
ncr53c400_log("NCR 53c400: Loaded?=%d, DMA mode enabled=%02x, valDMA=%02x.\n", ncr400->block_count_loaded, ncr->mode & MODE_DMA, val & MODE_DMA);
if (!ncr400->block_count_loaded) {
if (!(val & MODE_DMA)) {
ncr->tcr &= ~TCR_LAST_BYTE_SENT;
ncr->isr &= ~STATUS_END_OF_DMA;
scsi_bus->tx_mode = PIO_TX_BUS;
}
}
}
@@ -417,8 +423,13 @@ ncr53c400_callback(void *priv)
uint8_t temp;
uint8_t status;
if (scsi_bus->tx_mode != PIO_TX_BUS)
timer_on_auto(&ncr400->timer, 1.0);
if (scsi_bus->tx_mode != PIO_TX_BUS) {
if (ncr400->type == ROM_T130B) {
ncr53c400_log("PERIOD T130B DMA=%lf.\n", scsi_bus->period / 200.0);
timer_on_auto(&ncr400->timer, scsi_bus->period / 200.0);
} else
timer_on_auto(&ncr400->timer, 1.0);
}
if (scsi_bus->data_wait & 1) {
scsi_bus->clear_req = 3;
@@ -727,7 +738,6 @@ ncr53c400_init(const device_t *info)
scsi_bus->speed = 0.2;
scsi_bus->divider = 2.0;
scsi_bus->multi = 1.750;
return ncr400;
}