Merge branch 'master' into opti291
This commit is contained in:
nerd73
GitHub
@@ -1040,7 +1040,10 @@ piix_reset_hard(piix_t *dev)
|
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fregs[0x09] = 0x80;
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fregs[0x0a] = 0x01; fregs[0x0b] = 0x01;
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if (dev->type == 5) {
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||||
fregs[0x10] = fregs[0x14] = fregs[0x18] = fregs[0x1c] = 0x01;
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fregs[0x10] = 0xf1; fregs[0x11] = 0x01;
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fregs[0x14] = 0xf5; fregs[0x15] = 0x03;
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fregs[0x18] = 0x71; fregs[0x19] = 0x01;
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fregs[0x1c] = 0x75; fregs[0x1d] = 0x03;
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}
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fregs[0x20] = 0x01;
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if (dev->type == 5) {
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@@ -35,6 +35,9 @@
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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typedef struct
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{
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uint8_t index,
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@@ -43,54 +46,46 @@ typedef struct
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static void opti283_shadow_recalc(opti283_t *dev)
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{
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uint32_t base;
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uint32_t shflags, i = 0;
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uint32_t base, i;
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uint32_t shflagsc, shflagsd, shflagse, shflagsf;
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shadowbios = 0;
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shadowbios_write = 0;
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shadowbios = !(dev->regs[0x11] & 0x80);
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shadowbios_write = (dev->regs[0x11] & 0x80);
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if(dev->regs[0x11] & 0x10){
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shflagsc = MEM_READ_INTERNAL;
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shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagsc = disabled_shadow;
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if(dev->regs[0x11] & 0x20){
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shflagsd = MEM_READ_INTERNAL;
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shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagsd = disabled_shadow;
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if(dev->regs[0x11] & 0x40){
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shflagse = MEM_READ_INTERNAL;
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shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagse = disabled_shadow;
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/* F0000 - FFFFF segmentation */
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if(!(dev->regs[0x11] & 0x80)){
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shadowbios = 1;
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shadowbios_write = 0;
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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} else {
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shadowbios = 0;
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shadowbios_write = 1;
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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}
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shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
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} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
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mem_set_mem_state_both(0xf0000, 0x10000, shflagsf);
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/* C0000 - CFFFF segmentation */
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for(i = 4; i < 8; i++){
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base = 0xc0000 + ((i-4) << 14);
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if((dev->regs[0x13] & (1 << i)) & (dev->regs[0x11] & 0x10)){
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shflags = MEM_READ_INTERNAL;
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shflags |= (!(dev->regs[0x11] & 0x01)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
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mem_set_mem_state_both(base, 0x4000, shflags);
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} else {
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mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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base = 0xc0000 + ((i-4) << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow);
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}
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/* D0000 - DFFFF segmentation */
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for(i = 0; i < 4; i++){
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base = 0xd0000 + (i << 14);
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if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x20)){
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shflags = MEM_READ_INTERNAL;
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shflags |= (!(dev->regs[0x11] & 0x02)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
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mem_set_mem_state(base, 0x4000, shflags);
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} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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base = 0xd0000 + (i << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow);
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}
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/* E0000 - EFFFF segmentation */
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for(i = 4; i < 8; i++){
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base = 0xe0000 + ((i-4) << 14);
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if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x40)){
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shflags = MEM_READ_INTERNAL;
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shflags |= (!(dev->regs[0x11] & 0x04)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
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mem_set_mem_state(base, 0x4000, shflags);
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} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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base = 0xe0000 + ((i-4) << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow);
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}
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}
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@@ -105,12 +100,13 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
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dev->index = val;
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break;
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case 0x24:
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/*pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);*/
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/* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */
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dev->regs[dev->index] = val;
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switch(dev->index){
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case 0x10:
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cpu_update_waitstates();
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break;
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case 0x11:
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case 0x12:
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@@ -131,12 +131,13 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
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switch (addr) {
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case 0x22:
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opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val);
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dev->idx = val;
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break;
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case 0x24:
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2c)) {
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) {
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dev->regs[dev->idx] = val;
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opti495_log("dev->regs[%04x] = %08x\n", dev->idx, val);
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opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val);
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switch(dev->idx) {
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case 0x21:
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@@ -168,9 +169,14 @@ opti495_read(uint16_t addr, void *priv)
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opti495_t *dev = (opti495_t *) priv;
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switch (addr) {
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case 0x22:
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opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret);
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break;
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case 0x24:
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2c))
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) {
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ret = dev->regs[dev->idx];
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opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret);
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}
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break;
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case 0xe1:
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case 0xe2:
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@@ -197,6 +203,8 @@ opti495_init(const device_t *info)
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opti495_t *dev = (opti495_t *) malloc(sizeof(opti495_t));
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memset(dev, 0, sizeof(opti495_t));
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device_add(&port_92_device);
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io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
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@@ -45,35 +45,38 @@ static void
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opti5x7_recalc(opti5x7_t *dev)
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{
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uint32_t base;
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uint32_t i, j, shflags = 0;
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uint32_t i, shflags = 0;
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uint32_t reg, lowest_bit;
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uint32_t write = 0;
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shadowbios = 0;
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shadowbios_write = 0;
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for (i = 0; i < 8; i++) {
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j = i / 2.01; /*Probably not a great way of doing this, but it does work*/
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base = 0xc0000 + (j << 14);
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lowest_bit = j * 2;
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reg = 0x04 + ((base >> 16) & 0x01);
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shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state(base, 0x4000, shflags);
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base = 0xc0000 + (i << 14);
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lowest_bit = (i << 1) & 0x07;
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reg = 0x04 + ((base >> 16) & 0x01);
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shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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shadowbios |= !!(dev->regs[0x06] & 0x05);
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shadowbios_write |= !!(dev->regs[0x06] & 0x0a);
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shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[0x06] & 0x01) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xe0000, 0x10000, shflags);
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shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[0x06] & 0x04) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xf0000, 0x10000, shflags);
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flushmmucache();
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}
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static void
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opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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{
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@@ -90,7 +93,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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case 0x02:
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08);
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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@@ -138,9 +141,6 @@ opti5x7_init(const device_t *info)
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io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
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dev->port_92 = device_add(&port_92_device);
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// pclog("OPTi 5x7 init\n");
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opti5x7_recalc(dev);
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|
||||
|
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return dev;
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}
|
||||
|
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725
src/chipset/stpc.c
Normal file
725
src/chipset/stpc.c
Normal file
@@ -0,0 +1,725 @@
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||||
/*
|
||||
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
||||
* running old operating systems and software designed for IBM
|
||||
* PC systems and compatibles from 1981 through fairly recent
|
||||
* system designs based on the PCI bus.
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* Implementation of the STPC series of SoCs.
|
||||
*
|
||||
*
|
||||
*
|
||||
* Authors: RichardG, <richardg867@gmail.com>
|
||||
*
|
||||
* Copyright 2020 RichardG.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <wchar.h>
|
||||
#define HAVE_STDARG_H
|
||||
#include <86box/86box.h>
|
||||
#include <86box/mem.h>
|
||||
#include <86box/io.h>
|
||||
#include <86box/rom.h>
|
||||
#include <86box/pci.h>
|
||||
#include <86box/device.h>
|
||||
#include <86box/keyboard.h>
|
||||
#include <86box/port_92.h>
|
||||
#include <86box/usb.h>
|
||||
#include <86box/chipset.h>
|
||||
|
||||
|
||||
#define STPC_NB_CLIENT 0x01
|
||||
#define STPC_ISAB_CLIENT 0x02
|
||||
#define STPC_ISAB_CONSUMER2 0x04
|
||||
#define STPC_IDE_ATLAS 0x08
|
||||
#define STPC_USB 0x10
|
||||
|
||||
|
||||
typedef struct stpc_t
|
||||
{
|
||||
uint32_t local;
|
||||
|
||||
/* Main registers (port 22h/23h) */
|
||||
uint8_t reg_offset;
|
||||
uint8_t regs[256];
|
||||
|
||||
/* Host bus interface */
|
||||
uint16_t host_base;
|
||||
uint8_t host_offset;
|
||||
uint8_t host_regs[256];
|
||||
|
||||
/* Local bus */
|
||||
uint16_t localbus_base;
|
||||
uint8_t localbus_offset;
|
||||
uint8_t localbus_regs[256];
|
||||
|
||||
/* PCI devices */
|
||||
uint8_t pci_conf[4][256];
|
||||
usb_t *usb;
|
||||
} stpc_t;
|
||||
|
||||
|
||||
#define ENABLE_STPC_LOG 1
|
||||
#ifdef ENABLE_STPC_LOG
|
||||
int stpc_do_log = ENABLE_STPC_LOG;
|
||||
|
||||
|
||||
static void
|
||||
stpc_log(const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
if (stpc_do_log) {
|
||||
va_start(ap, fmt);
|
||||
pclog_ex(fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define stpc_log(fmt, ...)
|
||||
#endif
|
||||
|
||||
|
||||
static void
|
||||
stpc_recalcmapping(stpc_t *dev)
|
||||
{
|
||||
uint8_t reg, bitpair;
|
||||
uint32_t base, size;
|
||||
int state;
|
||||
|
||||
shadowbios = 0;
|
||||
shadowbios_write = 0;
|
||||
|
||||
for (reg = 0; reg <= 3; reg++) {
|
||||
for (bitpair = 0; bitpair <= (reg == 3 ? 0 : 3); bitpair++) {
|
||||
if (reg == 3) {
|
||||
size = 0x10000;
|
||||
base = 0xf0000;
|
||||
} else {
|
||||
size = 0x4000;
|
||||
base = 0xc0000 + (size * ((reg * 4) + bitpair));
|
||||
}
|
||||
stpc_log("STPC: Shadowing for %05x-%05x (reg %02x bp %d wmask %02x rmask %02x) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
|
||||
|
||||
state = 0;
|
||||
if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
|
||||
stpc_log(" w on");
|
||||
state |= MEM_WRITE_INTERNAL;
|
||||
if (base >= 0xe0000)
|
||||
shadowbios_write |= 1;
|
||||
} else {
|
||||
stpc_log(" w off");
|
||||
state |= MEM_WRITE_EXTANY;
|
||||
}
|
||||
if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
|
||||
stpc_log("; r on\n");
|
||||
state |= MEM_READ_INTERNAL;
|
||||
if (base >= 0xe0000)
|
||||
shadowbios |= 1;
|
||||
} else {
|
||||
stpc_log("; r off\n");
|
||||
state |= MEM_READ_EXTANY;
|
||||
}
|
||||
|
||||
mem_set_mem_state(base, size, state);
|
||||
}
|
||||
}
|
||||
|
||||
flushmmucache();
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
|
||||
{
|
||||
mem_set_mem_state_smram(smm, addr, size, is_smram);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_host_write(uint16_t addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: host_write(%04x, %02x)\n", addr, val);
|
||||
|
||||
if (addr == dev->host_base)
|
||||
dev->host_offset = val;
|
||||
else if (addr == dev->host_base + 4)
|
||||
dev->host_regs[dev->host_offset] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_host_read(uint16_t addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (addr == dev->host_base)
|
||||
ret = dev->host_offset;
|
||||
else if (addr == dev->host_base + 4)
|
||||
ret = dev->host_regs[dev->host_offset];
|
||||
else
|
||||
ret = 0xff;
|
||||
|
||||
stpc_log("STPC: host_read(%04x) = %02x\n", addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: localbus_write(%04x, %02x)\n", addr, val);
|
||||
|
||||
if (addr == dev->localbus_base)
|
||||
dev->localbus_offset = val;
|
||||
else if (addr == dev->localbus_base + 4)
|
||||
dev->localbus_regs[addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_localbus_read(uint16_t addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (addr == dev->localbus_base)
|
||||
ret = dev->localbus_offset;
|
||||
else if (addr == dev->localbus_base + 4)
|
||||
ret = dev->localbus_regs[dev->localbus_offset];
|
||||
else
|
||||
ret = 0xff;
|
||||
|
||||
stpc_log("STPC: localbus_read(%04x) = %02x\n", addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: nb_write(%d, %02x, %02x)\n", func, addr, val);
|
||||
|
||||
if (func > 0)
|
||||
return;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x04: case 0x06: case 0x07: case 0x08:
|
||||
case 0x09: case 0x0a: case 0x0b: case 0x0e:
|
||||
case 0x51: case 0x53: case 0x54:
|
||||
return;
|
||||
|
||||
case 0x05:
|
||||
val &= 0x01;
|
||||
break;
|
||||
|
||||
case 0x50:
|
||||
val &= 0x1f;
|
||||
break;
|
||||
|
||||
case 0x52:
|
||||
val &= 0x70;
|
||||
break;
|
||||
}
|
||||
|
||||
dev->pci_conf[0][addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_nb_read(int func, int addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (func > 0)
|
||||
ret = 0xff;
|
||||
else
|
||||
ret = dev->pci_conf[0][addr];
|
||||
|
||||
stpc_log("STPC: nb_read(%d, %02x) = %02x\n", func, addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_ide_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: ide_write(%d, %02x, %02x)\n", func, addr, val);
|
||||
|
||||
if (func > 0)
|
||||
return;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x04: case 0x06: case 0x07: case 0x08:
|
||||
case 0x09: case 0x0a: case 0x0b: case 0x0e:
|
||||
return;
|
||||
|
||||
case 0x05:
|
||||
val &= 0x01;
|
||||
break;
|
||||
}
|
||||
|
||||
dev->pci_conf[2][addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_ide_read(int func, int addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (func > 0)
|
||||
ret = 0xff;
|
||||
else
|
||||
ret = dev->pci_conf[2][addr];
|
||||
|
||||
stpc_log("STPC: ide_read(%d, %02x) = %02x\n", func, addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_isab_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) {
|
||||
stpc_ide_write(0, addr, val, priv);
|
||||
return;
|
||||
}
|
||||
|
||||
stpc_log("STPC: isab_write(%d, %02x, %02x)\n", func, addr, val);
|
||||
|
||||
if (func > 0)
|
||||
return;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x04: case 0x06: case 0x07: case 0x08:
|
||||
case 0x09: case 0x0a: case 0x0b: case 0x0e:
|
||||
return;
|
||||
|
||||
case 0x05:
|
||||
val &= 0x01;
|
||||
break;
|
||||
}
|
||||
|
||||
dev->pci_conf[1][addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_isab_read(int func, int addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (func == 1 && !(dev->local & STPC_IDE_ATLAS))
|
||||
return stpc_ide_read(0, addr, priv);
|
||||
else if (func > 0)
|
||||
ret = 0xff;
|
||||
else
|
||||
ret = dev->pci_conf[1][addr];
|
||||
|
||||
stpc_log("STPC: isab_read(%d, %02x) = %02x\n", func, addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_usb_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: usb_write(%d, %02x, %02x)\n", func, addr, val);
|
||||
|
||||
if (func > 0)
|
||||
return;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x04: case 0x06: case 0x07: case 0x08:
|
||||
case 0x09: case 0x0a: case 0x0b: case 0x0e:
|
||||
case 0x10:
|
||||
return;
|
||||
|
||||
case 0x05:
|
||||
val &= 0x01;
|
||||
break;
|
||||
|
||||
case 0x11:
|
||||
dev->pci_conf[3][addr] = val & 0xf0;
|
||||
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
|
||||
break;
|
||||
|
||||
case 0x12: case 0x13:
|
||||
dev->pci_conf[3][addr] = val;
|
||||
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
|
||||
break;
|
||||
}
|
||||
|
||||
dev->pci_conf[3][addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_usb_read(int func, int addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (func > 0)
|
||||
ret = 0xff;
|
||||
else
|
||||
ret = dev->pci_conf[3][addr];
|
||||
|
||||
stpc_log("STPC: usb_read(%d, %02x) = %02x\n", func, addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_remap_host(stpc_t *dev, uint16_t host_base)
|
||||
{
|
||||
stpc_log("STPC: Remapping host bus from %04x to %04x\n", dev->host_base, host_base);
|
||||
|
||||
io_removehandler(dev->host_base, 5,
|
||||
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
|
||||
if (host_base) {
|
||||
io_sethandler(host_base, 5,
|
||||
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
|
||||
}
|
||||
dev->host_base = host_base;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
|
||||
{
|
||||
stpc_log("STPC: Remapping local bus from %04x to %04x\n", dev->localbus_base, localbus_base);
|
||||
|
||||
io_removehandler(dev->localbus_base, 5,
|
||||
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
|
||||
if (localbus_base) {
|
||||
io_sethandler(localbus_base, 5,
|
||||
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
|
||||
}
|
||||
dev->localbus_base = localbus_base;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: reg_write(%04x, %02x)\n", addr, val);
|
||||
|
||||
if (addr == 0x22) {
|
||||
dev->reg_offset = val;
|
||||
} else {
|
||||
stpc_log("STPC: regs[%02x] = %02x\n", dev->reg_offset, val);
|
||||
|
||||
switch (dev->reg_offset) {
|
||||
case 0x12:
|
||||
if (dev->regs[0x10] == 0x07)
|
||||
stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
|
||||
else if (dev->regs[0x10] == 0x06)
|
||||
stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
|
||||
break;
|
||||
|
||||
case 0x13:
|
||||
if (dev->regs[0x10] == 0x07)
|
||||
stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
|
||||
else if (dev->regs[0x10] == 0x06)
|
||||
stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
|
||||
break;
|
||||
|
||||
case 0x21:
|
||||
val &= 0xfe;
|
||||
break;
|
||||
|
||||
case 0x22:
|
||||
val &= 0x7f;
|
||||
break;
|
||||
|
||||
case 0x25: case 0x26: case 0x27: case 0x28:
|
||||
if (dev->reg_offset == 0x28) {
|
||||
val &= 0xe3;
|
||||
stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
|
||||
}
|
||||
dev->regs[dev->reg_offset] = val;
|
||||
stpc_recalcmapping(dev);
|
||||
break;
|
||||
|
||||
case 0x29:
|
||||
val &= 0x0f;
|
||||
break;
|
||||
|
||||
case 0x36:
|
||||
val &= 0x3f;
|
||||
break;
|
||||
}
|
||||
|
||||
dev->regs[dev->reg_offset] = val;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
stpc_reg_read(uint16_t addr, void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
uint8_t ret;
|
||||
|
||||
if (addr == 0x22)
|
||||
ret = dev->reg_offset;
|
||||
else if (dev->reg_offset >= 0xc0)
|
||||
return 0xff; /* Cyrix CPU registers: let the CPU code handle those */
|
||||
else
|
||||
ret = dev->regs[dev->reg_offset];
|
||||
|
||||
stpc_log("STPC: reg_read(%04x) = %02x\n", addr, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_reset(void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: reset()\n");
|
||||
|
||||
memset(dev->regs, 0, sizeof(dev->regs));
|
||||
dev->regs[0x7b] = 0xff;
|
||||
|
||||
io_removehandler(0x22, 2,
|
||||
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
|
||||
io_sethandler(0x22, 2,
|
||||
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_setup(stpc_t *dev)
|
||||
{
|
||||
stpc_log("STPC: setup()\n");
|
||||
|
||||
/* Northbridge */
|
||||
dev->pci_conf[0][0x00] = 0x4a;
|
||||
dev->pci_conf[0][0x01] = 0x10;
|
||||
if (dev->local & STPC_NB_CLIENT) {
|
||||
dev->pci_conf[0][0x02] = 0x64;
|
||||
dev->pci_conf[0][0x03] = 0x05;
|
||||
} else {
|
||||
dev->pci_conf[0][0x02] = 0x0a;
|
||||
dev->pci_conf[0][0x03] = 0x02;
|
||||
}
|
||||
|
||||
dev->pci_conf[0][0x04] = 0x07;
|
||||
|
||||
dev->pci_conf[0][0x06] = 0x80;
|
||||
dev->pci_conf[0][0x07] = 0x02;
|
||||
|
||||
dev->pci_conf[0][0x0b] = 0x06;
|
||||
|
||||
/* ISA Bridge */
|
||||
dev->pci_conf[1][0x00] = 0x4a;
|
||||
dev->pci_conf[1][0x01] = 0x10;
|
||||
if (dev->local & STPC_ISAB_CLIENT) {
|
||||
dev->pci_conf[1][0x02] = 0xcc;
|
||||
dev->pci_conf[1][0x03] = 0x55;
|
||||
} else if (dev->local & STPC_ISAB_CONSUMER2) {
|
||||
dev->pci_conf[1][0x02] = 0x0b;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
} else {
|
||||
dev->pci_conf[1][0x02] = 0x10;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
}
|
||||
|
||||
dev->pci_conf[1][0x04] = 0x0f;
|
||||
|
||||
dev->pci_conf[1][0x06] = 0x80;
|
||||
dev->pci_conf[1][0x07] = 0x02;
|
||||
|
||||
dev->pci_conf[1][0x0a] = 0x01;
|
||||
dev->pci_conf[1][0x0b] = 0x06;
|
||||
|
||||
dev->pci_conf[1][0x0e] = 0x40;
|
||||
|
||||
/* IDE */
|
||||
dev->pci_conf[2][0x00] = 0x4a;
|
||||
dev->pci_conf[2][0x01] = 0x10;
|
||||
if (dev->local & STPC_IDE_ATLAS) {
|
||||
dev->pci_conf[2][0x02] = 0x28;
|
||||
dev->pci_conf[2][0x03] = 0x02;
|
||||
} else {
|
||||
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
|
||||
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
|
||||
}
|
||||
|
||||
dev->pci_conf[2][0x06] = 0x80;
|
||||
dev->pci_conf[2][0x07] = 0x02;
|
||||
|
||||
dev->pci_conf[2][0x09] = 0x8a;
|
||||
dev->pci_conf[2][0x0a] = 0x01;
|
||||
dev->pci_conf[2][0x0b] = 0x01;
|
||||
|
||||
dev->pci_conf[2][0x0e] = 0x40;
|
||||
|
||||
dev->pci_conf[2][0x10] = 0x01;
|
||||
dev->pci_conf[2][0x14] = 0x01;
|
||||
dev->pci_conf[2][0x18] = 0x01;
|
||||
dev->pci_conf[2][0x1c] = 0x01;
|
||||
|
||||
dev->pci_conf[2][0x40] = 0x60;
|
||||
dev->pci_conf[2][0x41] = 0x97;
|
||||
dev->pci_conf[2][0x42] = 0x60;
|
||||
dev->pci_conf[2][0x43] = 0x97;
|
||||
dev->pci_conf[2][0x44] = 0x60;
|
||||
dev->pci_conf[2][0x45] = 0x97;
|
||||
dev->pci_conf[2][0x46] = 0x60;
|
||||
dev->pci_conf[2][0x47] = 0x97;
|
||||
|
||||
/* USB */
|
||||
if (dev->usb) {
|
||||
dev->pci_conf[3][0x00] = 0x4a;
|
||||
dev->pci_conf[3][0x01] = 0x10;
|
||||
dev->pci_conf[3][0x02] = 0x30;
|
||||
dev->pci_conf[3][0x03] = 0x02;
|
||||
|
||||
dev->pci_conf[3][0x06] = 0x80;
|
||||
dev->pci_conf[3][0x07] = 0x02;
|
||||
|
||||
dev->pci_conf[3][0x09] = 0x10;
|
||||
dev->pci_conf[3][0x0a] = 0x03;
|
||||
dev->pci_conf[3][0x0b] = 0x0c;
|
||||
|
||||
dev->pci_conf[3][0x0e] = 0x40;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
stpc_close(void *priv)
|
||||
{
|
||||
stpc_t *dev = (stpc_t *) priv;
|
||||
|
||||
stpc_log("STPC: close()\n");
|
||||
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
stpc_init(const device_t *info)
|
||||
{
|
||||
stpc_log("STPC: init()\n");
|
||||
|
||||
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
|
||||
memset(dev, 0, sizeof(stpc_t));
|
||||
|
||||
dev->local = info->local;
|
||||
|
||||
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
|
||||
pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
|
||||
if (dev->local & STPC_IDE_ATLAS)
|
||||
pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
|
||||
if (dev->local & STPC_USB) {
|
||||
dev->usb = device_add(&usb_device);
|
||||
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
|
||||
}
|
||||
|
||||
stpc_setup(dev);
|
||||
stpc_reset(dev);
|
||||
|
||||
smram[0].host_base = 0x000a0000;
|
||||
smram[0].ram_base = 0x000a0000;
|
||||
smram[0].size = 0x00020000;
|
||||
|
||||
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
|
||||
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
|
||||
|
||||
stpc_smram_map(0, smram[0].host_base, smram[0].size, 0);
|
||||
stpc_smram_map(1, smram[0].host_base, smram[0].size, 1);
|
||||
|
||||
device_add(&port_92_pci_device);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
||||
const device_t stpc_client_device =
|
||||
{
|
||||
"STPC Client",
|
||||
DEVICE_PCI,
|
||||
STPC_NB_CLIENT | STPC_ISAB_CLIENT,
|
||||
stpc_init,
|
||||
stpc_close,
|
||||
stpc_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t stpc_consumer2_device =
|
||||
{
|
||||
"STPC Consumer-II",
|
||||
DEVICE_PCI,
|
||||
STPC_ISAB_CONSUMER2,
|
||||
stpc_init,
|
||||
stpc_close,
|
||||
stpc_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t stpc_elite_device =
|
||||
{
|
||||
"STPC Elite",
|
||||
DEVICE_PCI,
|
||||
0,
|
||||
stpc_init,
|
||||
stpc_close,
|
||||
stpc_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t stpc_atlas_device =
|
||||
{
|
||||
"STPC Atlas",
|
||||
DEVICE_PCI,
|
||||
STPC_IDE_ATLAS | STPC_USB,
|
||||
stpc_init,
|
||||
stpc_close,
|
||||
stpc_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
Reference in New Issue
Block a user