A couple of cleanups in hdc_ide.c
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@@ -2920,9 +2920,8 @@ ide_ter_init(const device_t *info)
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if (irq == -1)
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isapnp_add_card(ide_ter_pnp_rom, sizeof(ide_ter_pnp_rom),
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ide_pnp_config_changed, NULL, NULL, NULL, (void *) 2);
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} else {
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} else
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ide_board_init(2, irq, HDC_TERTIARY_BASE, HDC_TERTIARY_SIDE, 0, 0);
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}
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return (ide_boards[2]);
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}
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@@ -3004,10 +3003,10 @@ ide_init(const device_t *info)
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switch (info->local) {
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case 0 ... 5:
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ide_board_init(0, 14, 0x1f0, 0x3f6, info->local, info->flags);
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ide_board_init(0, HDC_PRIMARY_IRQ, HDC_PRIMARY_BASE, HDC_PRIMARY_SIDE, info->local, info->flags);
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if (info->local & 1)
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ide_board_init(1, 15, 0x170, 0x376, info->local, info->flags);
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ide_board_init(1, HDC_SECONDARY_IRQ, HDC_SECONDARY_BASE, HDC_SECONDARY_SIDE, info->local, info->flags);
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break;
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default:
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@@ -3122,8 +3121,8 @@ static void
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mcide_mca_write(const int port, const uint8_t val, void *priv)
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{
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mcide_t *dev = (mcide_t *) priv;
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uint16_t bases[4] = { 0x01f0, 0x0170, 0x01e8, 0x0168 };
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int irqs[4] = { 10, 11, 14, 15 };
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uint16_t bases[4] = { HDC_PRIMARY_BASE, HDC_SECONDARY_BASE, HDC_TERTIARY_BASE, HDC_QUATERNARY_BASE };
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int irqs[4] = { HDC_QUATERNARY_IRQ, HDC_TERTIARY_IRQ, HDC_PRIMARY_IRQ, HDC_SECONDARY_IRQ };
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if ((port >= 0x102) && (dev->pos_regs[port & 7] != val)) {
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ide_log("IDE: mcawr(%04x, %02x) pos[2]=%02x pos[3]=%02x\n",
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@@ -51,7 +51,6 @@ extern const device_t esdi_ps2_device; /* esdi_mca */
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extern const device_t ide_isa_device; /* isa_ide */
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extern const device_t ide_isa_2ch_device; /* isa_ide_2ch */
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extern const device_t ide_isa_2ch_opt_device; /* isa_ide_2ch_opt */
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extern const device_t ide_vlb_device; /* vlb_ide */
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extern const device_t ide_vlb_2ch_device; /* vlb_ide_2ch */
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extern const device_t ide_pci_device; /* pci_ide */
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@@ -25,17 +25,17 @@
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#define IDE_BUS_MAX 4
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#define IDE_CHAN_MAX 2
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#define HDC_PRIMARY_BASE 0x01F0
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#define HDC_PRIMARY_SIDE 0x03F6
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#define HDC_PRIMARY_BASE 0x01f0
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#define HDC_PRIMARY_SIDE 0x03f6
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#define HDC_PRIMARY_IRQ 14
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#define HDC_SECONDARY_BASE 0x0170
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#define HDC_SECONDARY_SIDE 0x0376
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#define HDC_SECONDARY_IRQ 15
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#define HDC_TERTIARY_BASE 0x01E8
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#define HDC_TERTIARY_SIDE 0x03EE
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#define HDC_TERTIARY_BASE 0x01e8
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#define HDC_TERTIARY_SIDE 0x03ee
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#define HDC_TERTIARY_IRQ 11
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#define HDC_QUATERNARY_BASE 0x0168
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#define HDC_QUATERNARY_SIDE 0x036E
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#define HDC_QUATERNARY_SIDE 0x036e
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#define HDC_QUATERNARY_IRQ 10
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enum {
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