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Merge branch 'master' of https://github.com/86Box/86Box into feature/968_new

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This commit is contained in:
OBattler
2020-12-19 12:25:08 +01:00
parent 55f83c2866 4cb2f96d09
commit e56c018c39
10 changed files with 684 additions and 462 deletions
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12
src/cpu/cpu.c
View File

@@ -353,8 +353,14 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
const CPU *cpu_s = &cpu_family->cpus[cpu];
if (machine_s->cpu_block & cpu_s->cpu_type) /* CPU type blocklist */
return 0;
/* Check CPU blocklist. */
if (machine_s->cpu_block) {
uint8_t i = 0;
while (machine_s->cpu_block[i]) {
if (machine_s->cpu_block[i++] == cpu_s->cpu_type)
return 0;
}
}
uint32_t bus_speed = cpu_s->rspeed / cpu_s->multi;
@@ -408,7 +414,7 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
} else if (cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86L) /* 6x86(L) */
multi = 3.0;
}
else if ((multi == 5.0) && (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
else if ((multi == 5.0) && (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
multi = 5.5;
else if ((multi == 6.0) && (machine_s->cpu_max_multi < 6.0)) /* K6-2(+) / K6-3(+) */
multi = 2.0;

4
src/cpu/cpu.h
View File

@@ -32,7 +32,7 @@ enum {
};
enum {
CPU_8088, /* 808x class CPUs */
CPU_8088 = 1, /* 808x class CPUs */
CPU_8086,
#ifdef USE_NEC_808X
CPU_V20, /* NEC 808x class CPUs - future proofing */
@@ -157,7 +157,7 @@ typedef struct {
const char *manufacturer;
const char *name;
const char *internal_name;
const CPU cpus[32];
const CPU *cpus;
} cpu_family_t;
typedef struct {

142
src/cpu/cpu_table.c
View File

@@ -69,11 +69,11 @@ FPU fpus_internal[] =
const cpu_family_t cpu_families[] = {
{
.package = CPU_PKG_8088, /* pcjr = only 4.77 */
.package = CPU_PKG_8088,
.manufacturer = "Intel",
.name = "8088",
.internal_name = "8088",
.cpus = {
.cpus = (const CPU[]) {
{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"8", CPU_8088, fpus_8088, 8000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
@@ -87,7 +87,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "8088",
.internal_name = "8088_europc",
.cpus = {
.cpus = (const CPU[]) {
{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"9.54", CPU_8088, fpus_8088, 9545456, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
@@ -98,7 +98,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "8086",
.internal_name = "8086",
.cpus = {
.cpus = (const CPU[]) {
{"7.16", CPU_8086, fpus_8088, 7159092, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"8", CPU_8086, fpus_8088, 8000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"9.54", CPU_8086, fpus_8088, 9545456, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
@@ -112,7 +112,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "80286",
.internal_name = "286",
.cpus = {
.cpus = (const CPU[]) {
{"6", CPU_286, fpus_80286, 6000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
{"8", CPU_286, fpus_80286, 8000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
{"10", CPU_286, fpus_80286, 10000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
@@ -127,7 +127,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i386SX",
.internal_name = "i386sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
@@ -140,7 +140,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am386SX",
.internal_name = "am386sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
@@ -153,7 +153,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i386DX",
.internal_name = "i386dx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386DX, fpus_80386, 16000000, 1, 5000, 0x0308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386DX, fpus_80386, 20000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
@@ -166,7 +166,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "RapidCAD",
.internal_name = "rapidcad",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_RAPIDCAD, fpus_internal, 25000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
{"33", CPU_RAPIDCAD, fpus_internal, 33333333, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
{"40", CPU_RAPIDCAD, fpus_internal, 40000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
@@ -177,7 +177,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am386DX",
.internal_name = "am386dx",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x0308, 0, 0, 0, 6,6,3,3, 4},
{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x0308, 0, 0, 0, 7,7,3,3, 5},
@@ -190,7 +190,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ALi",
.name = "M6117",
.internal_name = "m6117",
.cpus = { /* All timings and edx_reset values assumed. */
.cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */
{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
{"", 0}
@@ -202,7 +202,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "386SLC",
.internal_name = "ibm386slc",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_IBM386SLC, fpus_80386, 16000000, 1, 5000, 0xA301, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_IBM386SLC, fpus_80386, 20000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_IBM386SLC, fpus_80386, 25000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3},
@@ -213,7 +213,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486SLC",
.internal_name = "cx486slc",
.cpus = {
.cpus = (const CPU[]) {
{"20", CPU_486SLC, fpus_80386, 20000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
{"25", CPU_486SLC, fpus_80386, 25000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
{"33", CPU_486SLC, fpus_80386, 33333333, 1, 5000, 0x400, 0, 0x0000, 0, 6,6,3,3, 4},
@@ -224,7 +224,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486SRx2",
.internal_name = "cx486srx2",
.cpus = {
.cpus = (const CPU[]) {
{"32", CPU_486SLC, fpus_80386, 32000000, 2, 5000, 0x406, 0, 0x0006, 0, 6,6,6,6, 4},
{"40", CPU_486SLC, fpus_80386, 40000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6},
{"50", CPU_486SLC, fpus_80386, 50000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6},
@@ -235,7 +235,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC",
.internal_name = "ibm486slc",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_IBM486SLC, fpus_80386, 33333333, 1, 5000, 0xA401, 0, 0, 0, 6,6,3,3, 4},
{"", 0}
}
@@ -244,7 +244,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC2",
.internal_name = "ibm486slc2",
.cpus = {
.cpus = (const CPU[]) {
{"40", CPU_IBM486SLC, fpus_80386, 40000000, 2, 5000, 0xA421, 0, 0, 0, 7,7,6,6, 5},
{"50", CPU_IBM486SLC, fpus_80386, 50000000, 2, 5000, 0xA421, 0, 0, 0, 8,8,6,6, 6},
{"66", CPU_IBM486SLC, fpus_80386, 66666666, 2, 5000, 0xA421, 0, 0, 0, 12,12,6,6, 8},
@@ -255,7 +255,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC3",
.internal_name = "ibm486slc3",
.cpus = {
.cpus = (const CPU[]) {
{"60", CPU_IBM486SLC, fpus_80386, 60000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 7},
{"75", CPU_IBM486SLC, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9},
{"100", CPU_IBM486SLC, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12},
@@ -266,7 +266,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486BL2",
.internal_name = "ibm486bl2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_IBM486BL, fpus_80386, 50000000, 2, 5000, 0xA439, 0, 0, 0, 8,8,6,6, 6},
{"66", CPU_IBM486BL, fpus_80386, 66666666, 2, 5000, 0xA439, 0, 0, 0, 12,12,6,6, 8},
{"", 0}
@@ -276,7 +276,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486BL3",
.internal_name = "ibm486bl3",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_IBM486BL, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9},
{"100", CPU_IBM486BL, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12},
{"", 0}
@@ -286,7 +286,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DLC",
.internal_name = "cx486dlc",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_486DLC, fpus_80386, 25000000, 1, 5000, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3},
{"33", CPU_486DLC, fpus_80386, 33333333, 1, 5000, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4},
{"40", CPU_486DLC, fpus_80386, 40000000, 1, 5000, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5},
@@ -297,7 +297,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DRx2",
.internal_name = "cx486drx2",
.cpus = {
.cpus = (const CPU[]) {
{"32", CPU_486DLC, fpus_80386, 32000000, 2, 5000, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4},
{"40", CPU_486DLC, fpus_80386, 40000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
{"50", CPU_486DLC, fpus_80386, 50000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
@@ -309,7 +309,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486SX",
.internal_name = "i486sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
@@ -321,7 +321,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486SX2",
.internal_name = "i486sx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_i486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66 (Q0569)", CPU_i486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"", 0}
@@ -331,7 +331,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX",
.internal_name = "i486dx",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
@@ -342,7 +342,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX2",
.internal_name = "i486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"40", CPU_i486DX2, fpus_internal, 40000000, 2, 5000, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
@@ -353,7 +353,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX2",
.internal_name = "i486dx2_pc330",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"", 0}
@@ -363,7 +363,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "iDX4",
.internal_name = "idx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_iDX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"100", CPU_iDX4, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"", 0}
@@ -373,7 +373,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "iDX4 OverDrive",
.internal_name = "idx4_od",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_iDX4, fpus_internal, 75000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/
{"100", CPU_iDX4, fpus_internal, 100000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", 0}
@@ -383,7 +383,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p24t",
.cpus = {
.cpus = (const CPU[]) {
{"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", 0}
@@ -393,7 +393,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486SX",
.internal_name = "am486sx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -403,7 +403,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486SX2",
.internal_name = "am486sx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Am486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"66", CPU_Am486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
{"", 0}
@@ -413,7 +413,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX",
.internal_name = "am486dx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -423,7 +423,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX2",
.internal_name = "am486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Am486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"66", CPU_Am486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"80", CPU_Am486DX2, fpus_internal, 80000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
@@ -434,7 +434,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX4",
.internal_name = "am486dx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_Am486DX4, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"90", CPU_Am486DX4, fpus_internal, 90000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"100", CPU_Am486DX4, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
@@ -446,7 +446,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am5x86",
.internal_name = "am5x86",
.cpus = {
.cpus = (const CPU[]) {
{"P75", CPU_Am5x86, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"P75+", CPU_Am5x86, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
{"P90", CPU_Am5x86, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
@@ -457,7 +457,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486S",
.internal_name = "cx486s",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
@@ -467,7 +467,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX",
.internal_name = "cx486dx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -477,7 +477,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX2",
.internal_name = "cx486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Cx486DX2, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"66", CPU_Cx486DX2, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"80", CPU_Cx486DX2, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
@@ -488,7 +488,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX4",
.internal_name = "cx486dx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_Cx486DX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"100", CPU_Cx486DX4, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"", 0}
@@ -498,7 +498,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx5x86",
.internal_name = "cx5x86",
.cpus = {
.cpus = (const CPU[]) {
{"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
{"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
@@ -512,7 +512,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ST",
.name = "STPC-DX",
.internal_name = "stpc_dx",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_Cx486DX, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"75", CPU_Cx486DX, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -522,7 +522,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ST",
.name = "STPC-DX2",
.internal_name = "stpc_dx2",
.cpus = {
.cpus = (const CPU[]) {
{"133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", 0}
}
@@ -533,7 +533,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium",
.internal_name = "pentium_p5",
.cpus = {
.cpus = (const CPU[]) {
{"50 (Q0399)", CPU_PENTIUM, fpus_internal, 50000000, 1, 5000, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4,3,3, 6},
{"60", CPU_PENTIUM, fpus_internal, 60000000, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 7},
{"66", CPU_PENTIUM, fpus_internal, 66666666, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 8},
@@ -544,7 +544,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p54c_od5v",
.cpus = {
.cpus = (const CPU[]) {
{"100", CPU_PENTIUM, fpus_internal, 100000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8,6,6, 12},
{"120", CPU_PENTIUM, fpus_internal, 120000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 14},
{"133", CPU_PENTIUM, fpus_internal, 133333333, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 16},
@@ -555,7 +555,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium",
.internal_name = "pentium_p54c",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
@@ -572,7 +572,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium MMX",
.internal_name = "pentium_p55c",
.cpus = {
.cpus = (const CPU[]) {
{"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
@@ -583,7 +583,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Mobile Pentium MMX",
.internal_name = "pentium_tillamook",
.cpus = {
.cpus = (const CPU[]) {
{"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
@@ -599,7 +599,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p54c_od3v",
.cpus = {
.cpus = (const CPU[]) {
{"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15},
{"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2},
{"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20},
@@ -610,7 +610,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive MMX",
.internal_name = "pentium_p55c_od",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9},
{"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15},
{"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2},
@@ -624,7 +624,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip",
.internal_name = "winchip",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
@@ -643,7 +643,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip 2",
.internal_name = "winchip2",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9},
{"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
@@ -655,7 +655,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip 2A",
.internal_name = "winchip2a",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2},
{"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28},
@@ -669,7 +669,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K5 (5k86)",
.internal_name = "k5_5k86",
.cpus = {
.cpus = (const CPU[]) {
{"75 (P75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90 (P90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100 (P100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
@@ -685,7 +685,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K5 (SSA/5)",
.internal_name = "k5_ssa5",
.cpus = {
.cpus = (const CPU[]) {
{"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
@@ -698,7 +698,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6 (Model 6)",
.internal_name = "k6_m6",
.cpus = {
.cpus = (const CPU[]) {
{"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
@@ -709,7 +709,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6 (Model 7)",
.internal_name = "k6_m7",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
@@ -721,7 +721,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-2",
.internal_name = "k6_2",
.cpus = {
.cpus = (const CPU[]) {
{"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28},
{"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32},
{"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36},
@@ -743,7 +743,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-2+",
.internal_name = "k6_2p",
.cpus = {
.cpus = (const CPU[]) {
{"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
@@ -756,7 +756,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-III",
.internal_name = "k6_3",
.cpus = {
.cpus = (const CPU[]) {
{"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"", 0}
@@ -766,7 +766,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-III+",
.internal_name = "k6_3p",
.cpus = {
.cpus = (const CPU[]) {
{"100", CPU_K6_3P, fpus_internal, 100000000, 1.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
@@ -781,7 +781,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86",
.internal_name = "cx6x86",
.cpus = {
.cpus = (const CPU[]) {
{"P90", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"PR120+", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"PR133+", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
@@ -795,7 +795,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86L",
.internal_name = "cx6x86l",
.cpus = {
.cpus = (const CPU[]) {
{"PR133+", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"PR150+", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"PR166+", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
@@ -807,7 +807,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86MX",
.internal_name = "cx6x86mx",
.cpus = {
.cpus = (const CPU[]) {
{"PR166", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"PR200", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"PR233", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
@@ -819,7 +819,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "MII",
.internal_name = "mii",
.cpus = {
.cpus = (const CPU[]) {
{"PR300", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"PR333", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"PR366", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
@@ -834,7 +834,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium Pro",
.internal_name = "pentiumpro",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUMPRO, fpus_internal, 50000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUMPRO, fpus_internal, 60000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUMPRO, fpus_internal, 66666666, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -850,7 +850,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II OverDrive",
.internal_name = "pentium2_od",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2D, fpus_internal, 50000000, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2D, fpus_internal, 60000000, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8},
@@ -870,7 +870,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II (Klamath)",
.internal_name = "pentium2_klamath",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2, fpus_internal, 50000000, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2, fpus_internal, 60000000, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2, fpus_internal, 66666666, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -885,7 +885,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II (Deschutes)",
.internal_name = "pentium2_deschutes",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2D, fpus_internal, 50000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2D, fpus_internal, 60000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -903,7 +903,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II Xeon",
.internal_name = "pentium2_xeon",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUM2D, fpus_internal, 75000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
@@ -917,7 +917,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Celeron (Mendocino)",
.internal_name = "celeron_mendocino",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8},
{"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 10,10, 6, 6, 12},
{"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12, 6, 6, 16},
@@ -937,7 +937,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "VIA",
.name = "Cyrix III",
.internal_name = "c3_samuel",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_CYRIX3S, fpus_internal, 66666666, 1.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* not in multiplier range */
{"233", CPU_CYRIX3S, fpus_internal, 233333333, 3.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 21, 21, 9, 9, 28}, /* not in multiplier range */
{"266", CPU_CYRIX3S, fpus_internal, 266666666, 4.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 24, 24, 12, 12, 32}, /* not in multiplier range */

50
src/device/clock_ics9xxx.c
View File

@@ -78,7 +78,7 @@ typedef struct {
} hw_select;
uint8_t frequencies_ref; /* which other model to use the frequency table from (or 0) */
ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
const ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
} ics9xxx_model_t;
typedef struct {
@@ -105,7 +105,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0x6f, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
@@ -130,7 +130,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xfe, 0x7f, 0xff, 0xff, 0xb7},
.fs_regs = {{0, 4, 1, 0}, {0, 5, 2, 7}, {0, 6, 5, 6}, {0, 2, 5, 3}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 3},
{.bus = 6670, .ram_mult = 1.5, .pci_div = 2},
{.bus = 9500, .ram_mult = 2.0/3.0, .pci_div = 3},
@@ -155,7 +155,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
@@ -180,7 +180,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0x7f, 0xff, 0xbf, 0xf5, 0xff, 0x06},
.fs_regs = {{0, 4, 3, 6}, {0, 5, 4, 3}, {0, 6, 1, 7}, {0, 7, 4, 1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
@@ -221,7 +221,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xff, 0xff, 0xff, 0xf5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11499, .pci_div = 3},
@@ -253,7 +253,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0xff, 0xff, 0xec, 0xde, 0xff, 0x06},
.fs_regs = {{0, 4, 4, 5}, {0, 5, 3, 4}, {0, 6, 3, 0}, {0, 7, 3, 1}, {0, 2, 4, 0}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 10300, .pci_div = 3},
{.bus = 10000, .pci_div = 3},
{.bus = 10045, .pci_div = 3},
@@ -294,7 +294,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xfb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6800, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
@@ -335,7 +335,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x3f, 0x7f, 0x6f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 1, 6}, {0, 6, 1, 7}, {0, 7, 3, 4}, {0, 2, 3, 7}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6687, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6867, .ram_mult = 1.5, .pci_div = 2},
@@ -376,7 +376,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x6b, 0x7f, 0xff, 0xff, 0xe7, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 5, 3}, {0, 6, 1, 7}, {0, 7, 1, 4}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .pci_div = 3},
{.bus = 9500, .pci_div = 2},
{.bus = 10100, .pci_div = 2},
@@ -416,7 +416,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
@@ -441,7 +441,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x80, 0x4f, 0xff, 0x3f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, -1, -1}, {0, 5, -1, -1}, {0, 6, 3, 7}, {0, 1, 1, 4}, {0, 2, 1, 5}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 20000, .pci_div = 5, .agp_div = 2.5},
{.bus = 19000, .pci_div = 5, .agp_div = 2.5},
{.bus = 18000, .pci_div = 5, .agp_div = 2.5},
@@ -482,7 +482,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 7, -1, -1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
@@ -524,7 +524,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
@@ -550,7 +550,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x1f, 0xff, 0xfe, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {5, 4, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7067, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7466, .ram_mult = 1.5, .pci_div = 2},
@@ -575,7 +575,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xcf, 0x7f, 0xff, 0xff, 0xf7},
.fs_regs = {{0, 4, 1, 4}, {0, 5, 5, 7}, {0, 6, 1, 5}, {0, 2, 2, 7}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 2},
{.bus = 8901, .ram_mult = 1, .pci_div = 2},
{.bus = 8800, .ram_mult = 1, .pci_div = 2},
@@ -600,7 +600,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6781, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7201, .ram_mult = 1.5, .pci_div = 2},
@@ -641,7 +641,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x1f, 0xff, 0xff, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7267, .ram_mult = 1.5, .pci_div = 2},
@@ -667,7 +667,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
@@ -716,7 +716,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6900, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7100, .ram_mult = 1.5, .pci_div = 2},
@@ -757,7 +757,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
@@ -805,7 +805,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x0f, 0xff, 0xfe, 0x00, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {3, 0, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1.5, .pci_div = 2},
{.bus = 13332, .ram_mult = 1, .pci_div = 4},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
@@ -836,7 +836,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x0f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
@@ -882,7 +882,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x18, 0x07, 0xfe, 0xc7, 0xfc, 0x00, 0x80},
.fs_regs = {{0, 0, -1, -1}, {0, 1, -1, -1}, {0, 2, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.normal_bits_fixed = 1,
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1, .pci_div = 1},
{.bus = 10000, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 20000, .ram_mult = 1.0/3.0, .pci_div = 6},
@@ -899,7 +899,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x6f, 0xff, 0xff, 0xef, 0xff, 0x06},
.fs_regs = {{-1, -1, 1, 6}, {-1, -1, 4, 2}, {-1, -1, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
[0 ... 7] = {.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
[8 ... 15] = {.bus = 10000, .ram_mult = 1, .pci_div = 3},
[16 ... 23] = {.bus = 13333, .ram_mult = 1, .pci_div = 4},

4
src/device/hwm_gl518sm.c
View File

@@ -39,9 +39,9 @@ typedef struct {
hwm_values_t *values;
uint16_t regs[32];
uint8_t addr_register;
uint8_t addr_register: 5;
uint8_t i2c_addr, i2c_state;
uint8_t i2c_addr: 7, i2c_state: 2;
} gl518sm_t;

161
src/device/hwm_lm75.c
View File

@@ -30,12 +30,6 @@
#define LM75_TEMP_TO_REG(t) ((t) << 8)
static uint8_t lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
static uint8_t lm75_i2c_read(void *bus, uint8_t addr, void *priv);
static uint8_t lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
static void lm75_reset(lm75_t *dev);
#ifdef ENABLE_LM75_LOG
int lm75_do_log = ENABLE_LM75_LOG;
@@ -56,21 +50,6 @@ lm75_log(const char *fmt, ...)
#endif
void
lm75_remap(lm75_t *dev, uint8_t addr)
{
lm75_log("LM75: remapping to SMBus %02Xh\n", addr);
if (dev->i2c_addr < 0x80)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
dev->i2c_addr = addr;
}
static uint8_t
lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
@@ -82,49 +61,6 @@ lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm75_i2c_read(void *bus, uint8_t addr, void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal I2C call, if necessary. */
if ((dev->addr_register > 0x7) && ((dev->addr_register & 0xf8) != 0x50) && (dev->as99127f_i2c_addr < 0x80)) {
i2c_start(i2c_smbus, dev->as99127f_i2c_addr, 1);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, dev->addr_register);
ret = i2c_read(i2c_smbus, dev->as99127f_i2c_addr);
i2c_stop(i2c_smbus, dev->as99127f_i2c_addr);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x0 : 0x1);
break;
case 0x1: /* configuration */
ret = lm75_read(dev, 0x2);
break;
case 0x2: /* Thyst */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x3 : 0x4);
break;
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
}
}
if (++dev->i2c_state > 2)
dev->i2c_state = 2;
return ret;
}
uint8_t
lm75_read(lm75_t *dev, uint8_t reg)
{
@@ -143,6 +79,62 @@ lm75_read(lm75_t *dev, uint8_t reg)
}
static uint8_t
lm75_i2c_read(void *bus, uint8_t addr, void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
ret = lm78_as99127f_read(dev->as99127f, dev->addr_register);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x0 : 0x1);
break;
case 0x1: /* configuration */
ret = lm75_read(dev, 0x2);
break;
case 0x2: /* Thyst */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x3 : 0x4);
break;
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
}
}
if (dev->i2c_state < 2)
dev->i2c_state++;
return ret;
}
uint8_t
lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
{
lm75_log("LM75: write(%02X, %02X)\n", reg, val);
uint8_t reg_idx = (reg & 0x7);
if ((reg_idx <= 0x1) || (reg_idx == 0x7))
return 0; /* read-only registers */
dev->regs[reg_idx] = val;
return 1;
}
static uint8_t
lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
{
@@ -151,22 +143,18 @@ lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
if ((dev->i2c_state > 2) || ((dev->i2c_state == 2) && ((dev->addr_register & 0x3) == 0x1))) {
return 0;
} else if (dev->i2c_state == 0) {
dev->i2c_state = 1;
/* Linux lm75.c driver relies on the address register not changing if bit 2 is set. */
if ((dev->as99127f_i2c_addr < 0x80) || !(data & 0x04))
dev->i2c_state = 1;
/* Linux lm75.c driver relies on the address register not changing if bit 2 is set. */
if (((dev->addr_register & 0x80) && dev->as99127f) || !(data & 0x04))
dev->addr_register = data;
return 1;
}
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal I2C call, if necessary. */
if ((dev->addr_register > 0x7) && ((dev->addr_register & 0xf8) != 0x50) && (dev->as99127f_i2c_addr < 0x80)) {
i2c_start(i2c_smbus, dev->as99127f_i2c_addr, 0);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, dev->addr_register);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, data);
i2c_stop(i2c_smbus, dev->as99127f_i2c_addr);
return 1;
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
return lm78_as99127f_write(dev->as99127f, dev->addr_register, data);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
@@ -188,25 +176,24 @@ lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
}
if (dev->i2c_state == 1)
dev->i2c_state = 2;
dev->i2c_state = 2;
return 1;
}
uint8_t
lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
void
lm75_remap(lm75_t *dev, uint8_t addr)
{
lm75_log("LM75: write(%02X, %02X)\n", reg, val);
lm75_log("LM75: remapping to SMBus %02Xh\n", addr);
uint8_t reg_idx = (reg & 0x7);
if (dev->i2c_addr < 0x80)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
if ((reg_idx <= 0x1) || (reg_idx == 0x7))
return 0; /* read-only registers */
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
dev->regs[reg_idx] = val;
return 1;
dev->i2c_addr = addr;
}
@@ -244,8 +231,6 @@ lm75_init(const device_t *info)
hwm_values.temperatures[dev->local >> 8] = 30;
dev->values = &hwm_values;
dev->as99127f_i2c_addr = 0x80;
lm75_reset(dev);
return dev;

669
src/device/hwm_lm78.c
View File

@@ -25,6 +25,8 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/nvr.h>
#include "cpu.h"
#include <86box/i2c.h>
#include <86box/hwm.h>
@@ -48,28 +50,33 @@
typedef struct {
uint32_t local;
hwm_values_t *values;
device_t *lm75[2];
pc_timer_t hard_reset_timer;
uint32_t local;
hwm_values_t *values;
device_t *lm75[2];
pc_timer_t reset_timer;
uint8_t regs[256];
uint8_t regs_782d[2][16];
uint8_t addr_register;
uint8_t data_register;
uint8_t regs[256];
union {
struct {
uint8_t regs[2][16];
} w83782d;
struct {
uint8_t regs[3][128];
uint8_t i2c_addr, i2c_state;
uint8_t nvram[1024], nvram_i2c_state: 2, nvram_updated: 1;
uint16_t nvram_addr_register: 10;
int8_t nvram_block_len: 6;
uint8_t security_i2c_state: 1, security_addr_register: 7;
} as99127f;
};
uint8_t addr_register, data_register;
uint8_t i2c_addr: 7, i2c_state: 1;
} lm78_t;
static uint8_t lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
static uint8_t lm78_isa_read(uint16_t port, void *priv);
static uint8_t lm78_i2c_read(void *bus, uint8_t addr, void *priv);
static uint8_t lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank);
static void lm78_isa_write(uint16_t port, uint8_t val, void *priv);
static uint8_t lm78_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
static uint8_t lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank);
static void lm78_reset(lm78_t *dev, uint8_t initialization);
static void lm78_remap(lm78_t *dev, uint8_t addr);
#ifdef ENABLE_LM78_LOG
@@ -92,31 +99,223 @@ lm78_log(const char *fmt, ...)
#endif
static void
lm78_remap(lm78_t *dev, uint8_t addr)
void
lm78_nvram(lm78_t *dev, uint8_t save)
{
lm75_t *lm75;
size_t l = strlen(machine_get_internal_name_ex(machine)) + 1;
wchar_t *machine_name = (wchar_t *) malloc(l * sizeof(wchar_t));
mbstowcs(machine_name, machine_get_internal_name_ex(machine), l);
l = wcslen(machine_name) + 14;
wchar_t *nvr_path = (wchar_t *) malloc(l * sizeof(wchar_t));
swprintf(nvr_path, l, L"%ls_as99127f.nvr", machine_name);
if (!(dev->local & LM78_I2C)) return;
lm78_log("LM78: remapping to SMBus %02Xh\n", addr);
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
dev->i2c_addr = addr;
if (dev->local & LM78_AS99127F) {
/* Store the main I2C address on the LM75 devices to ensure reads/writes
to the AS99127F's proprietary registers are passed through to this side. */
for (uint8_t i = 0; i <= 1; i++) {
lm75 = device_get_priv(dev->lm75[i]);
if (lm75)
lm75->as99127f_i2c_addr = dev->i2c_addr;
}
FILE *f = nvr_fopen(nvr_path, save ? L"wb": L"rb");
if (f) {
if (save)
fwrite(&dev->as99127f.nvram, sizeof(dev->as99127f.nvram), 1, f);
else
fread(&dev->as99127f.nvram, sizeof(dev->as99127f.nvram), 1, f);
fclose(f);
}
free(machine_name);
free(nvr_path);
}
static uint8_t
lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
dev->as99127f.nvram_i2c_state = 0;
return 1;
}
static uint8_t
lm78_nvram_read(void *bus, uint8_t addr, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
uint8_t ret = 0xff;
switch (dev->as99127f.nvram_i2c_state) {
case 0:
dev->as99127f.nvram_i2c_state = 1;
/* fall-through */
case 1:
ret = dev->as99127f.regs[0][0x0b] & 0x3f;
lm78_log("LM78: nvram_read(blocklen) = %02X\n", ret);
break;
case 2:
ret = dev->as99127f.nvram[dev->as99127f.nvram_addr_register];
lm78_log("LM78: nvram_read(%03X) = %02X\n", dev->as99127f.nvram_addr_register, ret);
dev->as99127f.nvram_addr_register++;
break;
default:
lm78_log("LM78: nvram_read(unknown) = %02X\n", ret);
break;
}
if (dev->as99127f.nvram_i2c_state < 2)
dev->as99127f.nvram_i2c_state++;
return ret;
}
static uint8_t
lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (dev->as99127f.nvram_i2c_state) {
case 0:
lm78_log("LM78: nvram_write(address, %02X)\n", val);
dev->as99127f.nvram_addr_register = (addr << 8) | val;
break;
case 1:
lm78_log("LM78: nvram_write(blocklen, %02X)\n", val);
dev->as99127f.nvram_block_len = val & 0x3f;
if (dev->as99127f.nvram_block_len <= 0)
dev->as99127f.nvram_i2c_state = 3;
break;
case 2:
lm78_log("LM78: nvram_write(%03X, %02X)\n", dev->as99127f.nvram_addr_register, val);
dev->as99127f.nvram[dev->as99127f.nvram_addr_register++] = val;
dev->as99127f.nvram_updated = 1;
if (--dev->as99127f.nvram_block_len <= 0)
dev->as99127f.nvram_i2c_state = 3;
break;
default:
lm78_log("LM78: nvram_write(unknown, %02X)\n", val);
break;
}
if (dev->as99127f.nvram_i2c_state < 2)
dev->as99127f.nvram_i2c_state++;
return dev->as99127f.nvram_i2c_state < 3;
}
static uint8_t
lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
dev->as99127f.security_i2c_state = 0;
return 1;
}
static uint8_t
lm78_security_read(void *bus, uint8_t addr, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
return dev->as99127f.regs[2][dev->as99127f.security_addr_register++];
}
static uint8_t
lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->as99127f.security_i2c_state == 0) {
dev->as99127f.security_i2c_state = 1;
dev->as99127f.security_addr_register = val;
} else {
switch (dev->as99127f.security_addr_register) {
case 0xe0: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
/* read-only registers */
return 1;
}
dev->as99127f.regs[2][dev->as99127f.security_addr_register++] = val;
}
return 1;
}
static void
lm78_reset(lm78_t *dev, uint8_t initialization)
{
memset(dev->regs, 0, 256);
memset(dev->regs + 0xc0, 0xff, 32); /* C0-DF are 0xFF on a real AS99127F */
dev->regs[0x40] = 0x08;
dev->regs[0x46] = 0x40;
dev->regs[0x47] = 0x50;
if (dev->local & LM78_I2C) {
if (!initialization) /* don't reset main I2C address if the reset was triggered by the INITIALIZATION bit */
dev->i2c_addr = 0x2d;
dev->regs[0x48] = dev->i2c_addr;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x01;
} else {
dev->regs[0x48] = 0x00;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x88;
}
if (dev->local & LM78_WINBOND) {
dev->regs[0x49] = 0x02;
dev->regs[0x4b] = 0x44;
dev->regs[0x4c] = 0x01;
dev->regs[0x4d] = 0x15;
dev->regs[0x4e] = 0x80;
dev->regs[0x4f] = LM78_WINBOND_VENDOR_ID >> 8;
dev->regs[0x57] = 0x80;
if (dev->local & LM78_AS99127F) {
dev->regs[0x49] = 0x20;
dev->regs[0x4c] = 0x00;
dev->regs[0x56] = 0xff;
dev->regs[0x57] = 0xff;
dev->regs[0x58] = 0x31;
dev->regs[0x59] = 0x8f;
dev->regs[0x5a] = 0x8f;
dev->regs[0x5b] = 0x2a;
dev->regs[0x5c] = 0xe0;
dev->regs[0x5d] = 0x48;
dev->regs[0x5e] = 0xe2;
dev->regs[0x5f] = 0x1f;
dev->as99127f.regs[0][0x02] = 0xff;
dev->as99127f.regs[0][0x03] = 0xff;
dev->as99127f.regs[0][0x08] = 0xff;
dev->as99127f.regs[0][0x09] = 0xff;
dev->as99127f.regs[0][0x0b] = 0x01;
/* regs[1] and regs[2] start at 0x80 */
dev->as99127f.regs[1][0x00] = 0x88;
dev->as99127f.regs[1][0x01] = 0x10;
dev->as99127f.regs[1][0x04] = 0x01;
dev->as99127f.regs[1][0x05] = 0x1f;
lm78_as99127f_write(dev, 0x06, 0x2f);
dev->as99127f.regs[2][0x60] = 0xf0;
} else if (dev->local & LM78_W83781D) {
dev->regs[0x58] = 0x10;
} else if (dev->local & LM78_W83782D) {
dev->regs[0x58] = 0x30;
}
} else {
dev->regs[0x49] = 0x40;
}
lm78_remap(dev, dev->i2c_addr);
}
@@ -131,6 +330,53 @@ lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
{
uint8_t ret = 0, masked_reg = reg, bankswitched = ((reg & 0xf8) == 0x50);
lm75_t *lm75;
if ((dev->local & LM78_AS99127F) && (bank == 3) && (reg != 0x4e)) {
/* AS99127F additional registers */
if (!((dev->local & LM78_AS99127F_REV2) && ((reg == 0x80) || (reg == 0x81))))
ret = dev->as99127f.regs[0][reg & 0x7f];
} else if (bankswitched && ((bank == 1) || (bank == 2))) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
ret = lm75_read(lm75, reg);
} else if (bankswitched && ((bank == 4) || (bank == 5) || (bank == 6))) {
/* W83782D additional registers */
if (dev->local & LM78_W83782D) {
if ((bank == 5) && ((reg == 0x50) || (reg == 0x51))) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + (reg & 1)]);
else if (bank < 6)
ret = dev->w83782d.regs[bank - 4][reg & 0x0f];
}
} else {
/* regular registers */
if ((reg >= 0x60) && (reg <= 0x94)) /* read auto-increment value RAM registers from their non-auto-increment locations */
masked_reg = reg & 0x3f;
if ((masked_reg >= 0x20) && (masked_reg <= 0x26)) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[reg & 7]);
else if ((dev->local & LM78_AS99127F) && (masked_reg <= 0x05)) /* AS99127F additional voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + masked_reg]);
else if (masked_reg == 0x27) /* temperature */
ret = dev->values->temperatures[0];
else if ((masked_reg >= 0x28) && (masked_reg <= 0x2a)) /* fan speeds */
ret = LM78_RPM_TO_REG(dev->values->fans[reg & 3], 1 << ((dev->regs[((reg & 3) == 2) ? 0x4b : 0x47] >> ((reg & 3) ? 6 : 4)) & 0x3));
else if ((reg == 0x4f) && (dev->local & LM78_WINBOND)) /* two-byte vendor ID register */
ret = (dev->regs[0x4e] & 0x80) ? (LM78_WINBOND_VENDOR_ID >> 8) : LM78_WINBOND_VENDOR_ID;
else
ret = dev->regs[masked_reg];
}
lm78_log("LM78: read(%02X, %d) = %02X\n", reg, bank, ret);
return ret;
}
static uint8_t
lm78_isa_read(uint16_t port, void *priv)
{
@@ -139,7 +385,7 @@ lm78_isa_read(uint16_t port, void *priv)
switch (port & 0x7) {
case 0x5:
ret = (dev->addr_register & 0x7f);
ret = dev->addr_register & 0x7f;
break;
case 0x6:
@@ -147,7 +393,7 @@ lm78_isa_read(uint16_t port, void *priv)
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x7f)))) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x94)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
@@ -172,103 +418,18 @@ lm78_i2c_read(void *bus, uint8_t addr, void *priv)
}
static uint8_t
lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
uint8_t
lm78_as99127f_read(void *priv, uint8_t reg)
{
uint8_t ret = 0, masked_reg = reg, bankswitched = ((reg & 0xf8) == 0x50);
lm75_t *lm75;
lm78_t *dev = (lm78_t *) priv;
uint8_t ret = dev->as99127f.regs[1][reg & 0x7f];
if (bankswitched && ((bank == 1) || (bank == 2))) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
ret = lm75_read(lm75, reg);
} else if (bankswitched && ((bank == 4) || (bank == 5) || (bank == 6))) {
/* W83782D additional registers */
if (dev->local & LM78_W83782D) {
if ((bank == 5) && ((reg == 0x50) || (reg == 0x51))) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + (reg & 1)]);
else if (bank < 6)
ret = dev->regs_782d[bank - 4][reg & 0x0f];
}
} else {
/* regular registers */
ret = dev->regs[reg];
if (reg >= 0x40)
masked_reg = reg & 0x3f; /* match both non-auto-increment and auto-increment locations */
if ((masked_reg >= 0x20) && (masked_reg <= 0x26)) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[reg & 7]);
else if (masked_reg == 0x27) /* temperature */
ret = dev->values->temperatures[0];
else if ((masked_reg >= 0x28) && (masked_reg <= 0x2a)) /* fan speeds */
ret = LM78_RPM_TO_REG(dev->values->fans[reg & 3], 1 << ((dev->regs[((reg & 3) == 2) ? 0x4b : 0x47] >> ((reg & 3) ? 6 : 4)) & 0x3));
else if ((reg == 0x4f) && (dev->local & LM78_WINBOND)) /* two-byte vendor ID register */
ret = ((dev->regs[0x4e] & 0x80) ? (LM78_WINBOND_VENDOR_ID >> 8) : LM78_WINBOND_VENDOR_ID);
else if ((reg >= 0x60) && (reg <= 0x7f)) /* read auto-increment value RAM registers from their non-auto-increment locations */
ret = dev->regs[reg & 0x3f];
else if (dev->local & LM78_AS99127F) { /* AS99127F mirrored registers */
masked_reg = reg & 0x7f;
if (masked_reg == 0x00) /* IN2 Low Limit */
ret = dev->regs[0x30];
else if ((masked_reg == 0x01) || (masked_reg == 0x04)) /* IN3 */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[3]);
else if (masked_reg == 0x05) /* IN2 */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[2]);
else if (masked_reg == 0x08) /* IN3 Low Limit */
ret = dev->regs[0x32];
else if ((reg >= 0x80) && (reg <= 0x92)) /* mirror [0x00:0x12] to [0x80:0x92] */
ret = dev->regs[masked_reg];
}
}
lm78_log("LM78: read(%02X, %d) = %02X\n", reg, bank, ret);
lm78_log("LM78: read(%02X, AS99127F) = %02X\n", reg, ret);
return ret;
}
static void
lm78_isa_write(uint16_t port, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (port & 0x7) {
case 0x5:
dev->addr_register = (val & 0x7f);
break;
case 0x6:
lm78_write(dev, dev->addr_register, val, LM78_WINBOND_BANK);
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x7f)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
default:
lm78_log("LM78: Write %02X to unknown ISA port %d\n", val, port & 0x7);
break;
}
}
static uint8_t
lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->i2c_state == 0) {
dev->i2c_state = 1;
dev->addr_register = val;
} else
lm78_write(dev, dev->addr_register++, val, LM78_WINBOND_BANK);
return 1;
}
static uint8_t
lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
{
@@ -276,12 +437,27 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
lm78_log("LM78: write(%02X, %d, %02X)\n", reg, bank, val);
if ((reg & 0xf8) == 0x50) {
if ((dev->local & LM78_AS99127F) && (bank == 3) && (reg != 0x4e)) {
/* AS99127F additional registers */
reg &= 0x7f;
switch (reg) {
case 0x00: case 0x01: case 0x04: case 0x05: case 0x06: case 0x07:
/* read-only registers */
return 0;
case 0x20:
val &= 0x7f;
break;
}
dev->as99127f.regs[0][reg] = val;
return 1;
} else if ((reg & 0xf8) == 0x50) {
if ((bank == 1) || (bank == 2)) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
lm75_write(lm75, reg, val);
return lm75_write(lm75, reg, val);
return 1;
} else if (dev->local & LM78_W83782D) {
/* W83782D additional registers */
@@ -293,7 +469,7 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
return 0;
}
dev->regs_782d[0][reg & 0x0f] = val;
dev->w83782d.regs[0][reg & 0x0f] = val;
return 1;
} else if (bank == 5) {
switch (reg) {
@@ -303,19 +479,21 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
return 0;
}
dev->regs_782d[1][reg & 0x0f] = val;
dev->w83782d.regs[1][reg & 0x0f] = val;
return 1;
} else if (bank == 6) {
return 0;
}
}
}
}
/* regular registers */
switch (reg) {
case 0x41: case 0x42: case 0x4f: case 0x58:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2a:
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6a:
case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05:
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85:
/* read-only registers */
return 0;
@@ -326,12 +504,10 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
break;
}
if ((reg >= 0x60) && (reg <= 0x7f)) /* write auto-increment value RAM registers to their non-auto-increment locations */
dev->regs[reg & 0x3f] = val;
else if ((reg >= 0x80) && (reg <= 0x92)) /* AS99127F mirrors [0x00:0x12] to [0x80:0x92] */
dev->regs[reg & 0x7f] = val;
else
dev->regs[reg] = val;
if ((reg >= 0x60) && (reg <= 0x94)) /* write auto-increment value RAM registers to their non-auto-increment locations */
reg &= 0x3f;
uint8_t prev = dev->regs[reg];
dev->regs[reg] = val;
switch (reg) {
case 0x40:
@@ -363,26 +539,107 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
lm75 = device_get_priv(dev->lm75[i]);
if (!lm75)
continue;
if (dev->regs[0x4a] & (0x08 * (0x10 * i))) /* DIS_T2 and DIS_T3 bit disable those interfaces */
if (val & (0x08 * (0x10 * i))) /* DIS_T2 and DIS_T3 bit disable those interfaces */
lm75_remap(lm75, 0x80);
else
lm75_remap(lm75, 0x48 + ((dev->regs[0x4a] >> (i * 4)) & 0x7));
lm75_remap(lm75, 0x48 + ((val >> (i * 4)) & 0x7));
}
}
break;
case 0x81:
/* CUV4X-LS performs a hard reset through this register. */
if ((dev->local & LM78_AS99127F) && (val == 0xa9)) {
lm78_log("LM78: Hard reset requested through AS99127F\n");
timer_set_delay_u64(&dev->hard_reset_timer, 1); /* hard reset on a timer to avoid issues caused by invalidation of the I2C bus */
case 0x5c:
/* enable/disable AS99127F NVRAM */
if (dev->local & LM78_AS99127F) {
if (prev & 0x01)
i2c_removehandler(i2c_smbus, (prev & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
if (val & 0x01)
i2c_sethandler(i2c_smbus, (val & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
}
break;
}
return 1;
}
static void
lm78_isa_write(uint16_t port, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (port & 0x7) {
case 0x5:
dev->addr_register = val & 0x7f;
break;
case 0x6:
lm78_write(dev, dev->addr_register, val, LM78_WINBOND_BANK);
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x94)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
case 0x87:
/* Other AS99127F boards perform a soft reset through this register. */
if ((dev->local & LM78_AS99127F) && (val == 0x01)) {
lm78_log("LM78: Soft reset requested through AS99127F\n");
default:
lm78_log("LM78: Write %02X to unknown ISA port %d\n", val, port & 0x7);
break;
}
}
static uint8_t
lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->i2c_state == 0) {
dev->i2c_state = 1;
dev->addr_register = val;
} else
lm78_write(dev, dev->addr_register++, val, LM78_WINBOND_BANK);
return 1;
}
uint8_t
lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val)
{
lm78_t *dev = (lm78_t *) priv;
lm78_log("LM78: write(%02X, AS99127F, %02X)\n", reg, val);
reg &= 0x7f;
uint8_t prev = dev->as99127f.regs[1][reg];
dev->as99127f.regs[1][reg] = val;
switch (reg) {
case 0x01:
if (val & 0x40) {
dev->as99127f.regs[1][0x00] = 0x88;
dev->as99127f.regs[1][0x01] &= 0xe0;
dev->as99127f.regs[1][0x03] &= 0xf7;
dev->as99127f.regs[1][0x07] &= 0xfe;
}
if (!(val & 0x10)) { /* CUV4X-LS */
lm78_log("LM78: Reset requested through AS99127F CLKRST\n");
timer_set_delay_u64(&dev->reset_timer, 300000 * TIMER_USEC);
}
break;
case 0x06:
/* security device I2C address */
i2c_removehandler(i2c_smbus, prev & 0x7f, 1, lm78_security_start, lm78_security_read, lm78_security_write, NULL, dev);
i2c_sethandler(i2c_smbus, val & 0x7f, 1, lm78_security_start, lm78_security_read, lm78_security_write, NULL, dev);
break;
case 0x07:
if (val & 0x01) { /* other AS99127F boards */
lm78_log("LM78: Reset requested through AS99127F GPO15\n");
resetx86();
}
break;
@@ -393,79 +650,34 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
static void
lm78_hard_reset_timer(void *priv)
lm78_reset_timer(void *priv)
{
pc_reset_hard();
}
static void
lm78_reset(lm78_t *dev, uint8_t initialization)
lm78_remap(lm78_t *dev, uint8_t addr)
{
memset(dev->regs, 0, 256);
memset(dev->regs + 0xc0, 0xff, 32); /* C0-DF are 0xFF at least on the AS99127F */
lm75_t *lm75;
dev->regs[0x40] = 0x08;
dev->regs[0x46] = 0x40;
dev->regs[0x47] = 0x50;
if (dev->local & LM78_I2C) {
if (!initialization) /* don't reset main I2C address if the reset was triggered by the INITIALIZATION bit */
dev->i2c_addr = 0x2d;
dev->regs[0x48] = dev->i2c_addr;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x01;
} else {
dev->regs[0x48] = 0x00;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x88;
if (!(dev->local & LM78_I2C)) return;
lm78_log("LM78: remapping to SMBus %02Xh\n", addr);
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
dev->i2c_addr = addr;
if (dev->local & LM78_AS99127F) {
/* Store our handle on the primary LM75 device to ensure reads/writes
to the AS99127F's proprietary registers are passed through to this side. */
if ((lm75 = device_get_priv(dev->lm75[0])))
lm75->as99127f = dev;
}
if (dev->local & LM78_WINBOND) {
dev->regs[0x49] = 0x02;
dev->regs[0x4b] = 0x44;
dev->regs[0x4c] = 0x01;
dev->regs[0x4d] = 0x15;
dev->regs[0x4e] = 0x80;
dev->regs[0x4f] = (LM78_WINBOND_VENDOR_ID >> 8);
dev->regs[0x57] = 0x80;
/* Initialize proprietary registers on the AS99127F. The BIOS accesses some
of these on boot through read_byte_cmd on the TEMP2 address, hanging on
POST code C1 if they're defaulted to 0. There's no documentation on what
these are for. The following values were dumped from a live, initialized
AS99127F Rev. 2 on a P4B motherboard, and they seem to work well enough. */
if (dev->local & LM78_AS99127F) {
/* 0x00 appears to mirror IN2 Low Limit */
/* 0x01 appears to mirror IN3 */
dev->regs[0x02] = LM78_VOLTAGE_TO_REG(2800); /* appears to be a "maximum VCORE" of some kind; must read 2.8V on P3 boards */
dev->regs[0x03] = 0x60;
/* 0x04 appears to mirror IN3 */
/* 0x05 appears to mirror IN2 */
dev->regs[0x07] = 0xcd;
/* 0x08 appears to mirror IN3 Low Limit */
dev->regs[0x09] = dev->regs[0x0f] = dev->regs[0x11] = 0xf8; /* three instances of */
dev->regs[0x0a] = dev->regs[0x10] = dev->regs[0x12] = 0xa5; /* the same word */
dev->regs[0x0b] = 0xac;
dev->regs[0x0c] = 0x8c;
dev->regs[0x0d] = 0x68;
dev->regs[0x0e] = 0x54;
dev->regs[0x53] = dev->regs[0x54] = dev->regs[0x55] = 0xff;
dev->regs[0x58] = 0x31;
dev->regs[0x59] = dev->regs[0x5a] = 0x8f;
dev->regs[0x5c] = 0xe0;
dev->regs[0x5d] = 0x48;
dev->regs[0x5e] = 0xe2;
dev->regs[0x5f] = 0x3f;
} else if (dev->local & LM78_W83781D) {
dev->regs[0x58] = 0x10;
} else if (dev->local & LM78_W83782D) {
dev->regs[0x58] = 0x30;
}
} else {
dev->regs[0x49] = 0x40;
}
lm78_remap(dev, dev->i2c_addr);
}
@@ -478,6 +690,9 @@ lm78_close(void *priv)
if (isa_io)
io_removehandler(isa_io, 8, lm78_isa_read, NULL, NULL, lm78_isa_write, NULL, NULL, dev);
if (dev->as99127f.nvram_updated)
lm78_nvram(dev, 1);
free(dev);
}
@@ -508,17 +723,23 @@ lm78_init(const device_t *info)
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
LM78_NEG_VOLTAGE(12000, 2100), /* -12V */
LM78_NEG_VOLTAGE(5000, 909), /* -5V */
RESISTOR_DIVIDER(5000, 51, 75), /* W83782D only: +5VSB (5.1K/7.5K divider suggested in the datasheet) */
3000 /* W83782D only: Vbat */
RESISTOR_DIVIDER(5000, 51, 75), /* W83782D/AS99127F only: +5VSB (5.1K/7.5K divider suggested in the datasheet) */
3000, /* W83782D/AS99127F only: Vbat */
2500, /* AS99127F only: +2.5V */
1500, /* AS99127F only: +1.5V */
3000, /* AS99127F only: NVRAM */
3300 /* AS99127F only: +3.3VSB */
}
};
/* Set chip-specific default values. */
if (dev->local & LM78_AS99127F) {
/* AS99127: different -12V Rin value (bruteforced) */
/* AS99127F: different -12V Rin value (bruteforced) */
defaults.voltages[5] = LM78_NEG_VOLTAGE(12000, 2400);
timer_add(&dev->hard_reset_timer, lm78_hard_reset_timer, dev, 0);
timer_add(&dev->reset_timer, lm78_reset_timer, dev, 0);
lm78_nvram(dev, 0);
} else if (dev->local & LM78_W83782D) {
/* W83782D: different negative voltage formula */
defaults.voltages[5] = LM78_NEG_VOLTAGE2(12000, 232);
@@ -574,8 +795,8 @@ const device_t w83781d_device = {
};
/* The ASUS AS99127F is a customized W83781D with no ISA interface (I2C
only), added proprietary registers and different chip/vendor IDs. */
/* The AS99127F is an ASIC manufactured by Holtek for ASUS, containing an
I2C-only W83781D clone with additional voltages, GPIOs and fan control. */
const device_t as99127f_device = {
"ASUS AS99127F Rev. 1 Hardware Monitor",
DEVICE_ISA,
@@ -586,7 +807,7 @@ const device_t as99127f_device = {
};
/* Rev. 2 changes the vendor ID back to Winbond's and brings some other changes. */
/* Rev. 2 is manufactured by Winbond and differs only in GPI registers. */
const device_t as99127f_rev2_device = {
"ASUS AS99127F Rev. 2 Hardware Monitor",
DEVICE_ISA,

21
src/include/86box/hwm.h
View File

@@ -25,28 +25,33 @@
typedef struct {
uint16_t fans[4];
uint8_t temperatures[4];
uint16_t voltages[10];
uint16_t voltages[13];
} hwm_values_t;
typedef struct {
uint32_t local;
uint32_t local;
hwm_values_t *values;
void *as99127f;
uint8_t regs[8];
uint8_t addr_register;
uint8_t temp_idx;
uint8_t i2c_addr, i2c_state;
uint8_t as99127f_i2c_addr;
uint8_t regs[8];
uint8_t addr_register;
uint8_t i2c_addr: 7, i2c_state: 2;
} lm75_t;
/* hwm.c */
extern uint16_t hwm_get_vcore();
/* hwm_lm75.c */
extern void lm75_remap(lm75_t *dev, uint8_t addr);
extern uint8_t lm75_read(lm75_t *dev, uint8_t reg);
extern uint8_t lm75_write(lm75_t *dev, uint8_t reg, uint8_t val);
/* hwm_lm78.c */
extern uint8_t lm78_as99127f_read(void *priv, uint8_t reg);
extern uint8_t lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val);
/* hwm_vt82c686.c */
extern void vt82c686_hwm_write(uint8_t addr, uint8_t val, void *priv);

3
src/include/86box/machine.h
View File

@@ -85,6 +85,7 @@
#define IS_ARCH(m, a) (machines[m].flags & (a)) ? 1 : 0;
#define IS_AT(m) ((machines[m].flags & 0x00000FC8) && !(machines[m].flags & MACHINE_PC98)) ? 1 : 0;
#define CPU_BLOCK(...) (const uint8_t[]) {__VA_ARGS__, 0}
#define MACHINE_MULTIPLIER_FIXED -1, -1
@@ -145,7 +146,7 @@ typedef struct _machine_ {
const char *internal_name;
const char type;
uint32_t cpu_package;
uint64_t cpu_block;
const uint8_t *cpu_block;
uint32_t cpu_min_bus;
uint32_t cpu_max_bus;
uint16_t cpu_min_voltage;

80
src/machine/machine_table.c
View File

@@ -34,23 +34,23 @@
const machine_type_t machine_types[] = {
{ "None", MACHINE_TYPE_NONE },
{ "8088", MACHINE_TYPE_8088 },
{ "8086", MACHINE_TYPE_8086 },
{ "80286", MACHINE_TYPE_286 },
{ "i386SX", MACHINE_TYPE_386SX },
{ "i386DX", MACHINE_TYPE_386DX },
{ "i486", MACHINE_TYPE_486 },
{ "Socket 4", MACHINE_TYPE_SOCKET4 },
{ "Socket 5", MACHINE_TYPE_SOCKET5 },
{ "Socket 7-3V", MACHINE_TYPE_SOCKET7_3V },
{ "Socket 7", MACHINE_TYPE_SOCKET7 },
{ "Super Socket 7", MACHINE_TYPE_SOCKETS7 },
{ "Socket 8", MACHINE_TYPE_SOCKET8 },
{ "Slot 1", MACHINE_TYPE_SLOT1 },
{ "Slot 2", MACHINE_TYPE_SLOT2 },
{ "Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC }
{ "None", MACHINE_TYPE_NONE },
{ "8088", MACHINE_TYPE_8088 },
{ "8086", MACHINE_TYPE_8086 },
{ "80286", MACHINE_TYPE_286 },
{ "i386SX", MACHINE_TYPE_386SX },
{ "i386DX", MACHINE_TYPE_386DX },
{ "i486", MACHINE_TYPE_486 },
{ "Socket 4", MACHINE_TYPE_SOCKET4 },
{ "Socket 5", MACHINE_TYPE_SOCKET5 },
{ "Socket 7 (Single Voltage)", MACHINE_TYPE_SOCKET7_3V },
{ "Socket 7 (Dual Voltage)", MACHINE_TYPE_SOCKET7 },
{ "Super Socket 7", MACHINE_TYPE_SOCKETS7 },
{ "Socket 8", MACHINE_TYPE_SOCKET8 },
{ "Slot 1", MACHINE_TYPE_SLOT1 },
{ "Slot 2", MACHINE_TYPE_SLOT2 },
{ "Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC }
};
@@ -67,8 +67,8 @@ const machine_t machines[] = {
{ "[8088] DTK XT clone", "dtk", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] Generic XT clone", "genxt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] Juko XT clone", "jukopc", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] NCR PC4i", "ncr_pc4i", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 256, 640, 256, 0, machine_xt_ncrpc4i_init, NULL },
{ "[8088] Olivetti M19", "olivetti_m19", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 256, 640, 256, 0, machine_xt_olim19_init, NULL },
{ "[8088] NCR PC4i", "ncr_pc4i", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 256, 640, 256, 0, machine_xt_ncrpc4i_init, NULL },
{ "[8088] Olivetti M19", "olivetti_m19", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 256, 640, 256, 0, machine_xt_olim19_init, NULL },
{ "[8088] OpenXT", "open_xt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_open_xt_init, NULL },
{ "[8088] Phoenix XT clone", "pxxt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_pxxt_init, NULL },
{ "[8088] Schneider EuroPC", "europc", MACHINE_TYPE_8088, CPU_PKG_8088_EUROPC, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_XTA | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
@@ -88,8 +88,8 @@ const machine_t machines[] = {
{ "[8086] Amstrad PC3086", "pc3086", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 640, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M21/24/24SP", "olivetti_m24", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_xt_olim24_init, m24_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M21/24/24SP", "olivetti_m24", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_xt_olim24_init, m24_get_device },
{ "[8086] Olivetti M240", "olivetti_m240", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_olim240_init, NULL },
{ "[8086] Schetmash Iskra-3104", "iskra3104", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_iskra3104_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, tandy1k_sl_get_device },
@@ -230,20 +230,20 @@ const machine_t machines[] = {
/* Socket 4 machines */
/* 430LX */
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 139264, 2048, 127, machine_at_pb520r_init, at_pb520r_get_device },
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 139264, 2048, 127, machine_at_pb520r_init, at_pb520r_get_device },
/* OPTi 596/597 */
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
/* Socket 5 machines */
/* 430NX */
@@ -260,10 +260,10 @@ const machine_t machines[] = {
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_PENTIUMMMX), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
/* Socket 7 machines */
/* Socket 7 (Single Voltage) machines */
/* 430FX */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54tp4xe_init, NULL },
{ "[i430FX] ASUS P/I-P54TP4XE (MR BIOS)", "mr586", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mr586_init, NULL },
@@ -272,7 +272,7 @@ const machine_t machines[] = {
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_mrthor_init, NULL },
{ "[i430FX] Intel Advanced/EV", "endeavor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[i430FX] Packard Bell PB640", "pb640", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_WINCHIP|CPU_WINCHIP2|CPU_Cx6x86|CPU_Cx6x86L|CPU_Cx6x86MX, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_chariot_init, NULL },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX), 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_chariot_init, NULL },
/* 430HX */
{ "[i430HX] Acer M3A", "acerm3a", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerm3a_init, NULL },
@@ -280,7 +280,12 @@ const machine_t machines[] = {
{ "[i430HX] Biostar MB-8500TUC", "8500tuc", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_8500tuc_init, NULL },
{ "[i430HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 127, machine_at_p55t2s_init, NULL },
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, CPU_Cx6x86MX, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerv35n_init, NULL },
/* 430VX */
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_gw2kte_init, NULL },
/* Socket 7 (Dual Voltage) machines */
/* 430HX */
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_Cx6x86MX), 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerv35n_init, NULL },
{ "[i430HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_p55t2p4_init, NULL },
{ "[i430HX] Micronics M7S-Hi", "m7shi", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 511, machine_at_m7shi_init, NULL },
{ "[i430HX] Intel TC430HX", "tc430hx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 255, machine_at_tc430hx_init, NULL },
@@ -293,7 +298,6 @@ const machine_t machines[] = {
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_8500tvxa_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55va_init, NULL },
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_gw2kte_init, NULL },
{ "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 66666667, 66666667, 2200, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_brio80xx_init, NULL },
{ "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_pb680_init, NULL },
{ "[i430VX] Shuttle HOT-557", "430vx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_i430vx_init, NULL },
@@ -397,7 +401,7 @@ const machine_t machines[] = {
{ "[VIA Apollo ProMedia] Jetway 603TCF", "603tcf", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_603tcf_init, NULL },
/* Miscellaneous/Fake/Hypervisor machines */
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, CPU_PKG_SLOT1, CPU_PENTIUM2 | CPU_CYRIX3S, 0, 0, 0, 0, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vpc2007_init, NULL },
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, CPU_PKG_SLOT1, CPU_BLOCK(CPU_PENTIUM2, CPU_CYRIX3S), 0, 0, 0, 0, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vpc2007_init, NULL },
{ NULL, NULL, MACHINE_TYPE_NONE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL }
};