claunia/86Box
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clang-format in src/

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This commit is contained in:
Jasmine Iwanek
2022-09-18 17:11:43 -04:00
parent 2267153edd
commit e6dbaefeb1
35 changed files with 7113 additions and 7387 deletions
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151
src/port_92.c
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@@ -30,50 +30,45 @@
#include <86box/pit.h>
#include <86box/port_92.h>
#define PORT_92_INV 1
#define PORT_92_WORD 2
#define PORT_92_PCI 4
#define PORT_92_RESET 8
#define PORT_92_A20 16
#define PORT_92_INV 1
#define PORT_92_WORD 2
#define PORT_92_PCI 4
#define PORT_92_RESET 8
#define PORT_92_A20 16
static uint8_t
port_92_readb(uint16_t port, void *priv)
{
uint8_t ret = 0x00;
uint8_t ret = 0x00;
port_92_t *dev = (port_92_t *) priv;
if (port == 0x92) {
/* Return bit 1 directly from mem_a20_alt, so the
pin can be reset independently of the device. */
ret = (dev->reg & ~0x03) | (mem_a20_alt & 2) |
(cpu_alt_reset & 1);
/* Return bit 1 directly from mem_a20_alt, so the
pin can be reset independently of the device. */
ret = (dev->reg & ~0x03) | (mem_a20_alt & 2) | (cpu_alt_reset & 1);
if (dev->flags & PORT_92_INV)
ret |= 0xfc;
else if (dev->flags & PORT_92_PCI)
ret |= 0x24; /* Intel SIO datasheet says bits 2 and 5 are always 1. */
if (dev->flags & PORT_92_INV)
ret |= 0xfc;
else if (dev->flags & PORT_92_PCI)
ret |= 0x24; /* Intel SIO datasheet says bits 2 and 5 are always 1. */
} else if (dev->flags & PORT_92_INV)
ret = 0xff;
ret = 0xff;
return ret;
}
static uint16_t
port_92_readw(uint16_t port, void *priv)
{
uint16_t ret = 0xffff;
uint16_t ret = 0xffff;
port_92_t *dev = (port_92_t *) priv;
if (!(dev->flags & PORT_92_PCI))
ret = port_92_readb(port, priv);
ret = port_92_readb(port, priv);
return ret;
}
static void
port_92_pulse(void *priv)
{
@@ -81,44 +76,41 @@ port_92_pulse(void *priv)
cpu_set_edx();
}
static void
port_92_writeb(uint16_t port, uint8_t val, void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (port != 0x92)
return;
return;
dev->reg = val & 0x03;
if ((mem_a20_alt ^ val) & 2) {
mem_a20_alt = (val & 2);
mem_a20_recalc();
mem_a20_alt = (val & 2);
mem_a20_recalc();
}
if ((~cpu_alt_reset & val) & 1)
timer_set_delay_u64(&dev->pulse_timer, dev->pulse_period);
timer_set_delay_u64(&dev->pulse_timer, dev->pulse_period);
else if (!(val & 1))
timer_disable(&dev->pulse_timer);
timer_disable(&dev->pulse_timer);
cpu_alt_reset = (val & 1);
if (dev->flags & PORT_92_INV)
dev->reg |= 0xfc;
dev->reg |= 0xfc;
}
static void
port_92_writew(uint16_t port, uint16_t val, void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (!(dev->flags & PORT_92_PCI))
port_92_writeb(port, val & 0xff, priv);
port_92_writeb(port, val & 0xff, priv);
}
void
port_92_set_period(void *priv, uint64_t pulse_period)
{
@@ -127,7 +119,6 @@ port_92_set_period(void *priv, uint64_t pulse_period)
dev->pulse_period = pulse_period;
}
void
port_92_set_features(void *priv, int reset, int a20)
{
@@ -136,48 +127,45 @@ port_92_set_features(void *priv, int reset, int a20)
dev->flags &= ~(PORT_92_RESET | PORT_92_A20);
if (reset)
dev->flags |= PORT_92_RESET;
dev->flags |= PORT_92_RESET;
timer_disable(&dev->pulse_timer);
if (a20) {
dev->flags |= PORT_92_A20;
mem_a20_alt = (dev->reg & 2);
dev->flags |= PORT_92_A20;
mem_a20_alt = (dev->reg & 2);
} else
mem_a20_alt = 0;
mem_a20_alt = 0;
mem_a20_recalc();
}
void
port_92_add(void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (dev->flags & (PORT_92_WORD | PORT_92_PCI))
io_sethandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
io_sethandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
else
io_sethandler(0x0092, 1,
port_92_readb, NULL, NULL, port_92_writeb, NULL, NULL, dev);
io_sethandler(0x0092, 1,
port_92_readb, NULL, NULL, port_92_writeb, NULL, NULL, dev);
}
void
port_92_remove(void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (dev->flags & (PORT_92_WORD | PORT_92_PCI))
io_removehandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
io_removehandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
else
io_removehandler(0x0092, 1,
port_92_readb, NULL, NULL, port_92_writeb, NULL, NULL, dev);
io_removehandler(0x0092, 1,
port_92_readb, NULL, NULL, port_92_writeb, NULL, NULL, dev);
}
static void
port_92_close(void *priv)
{
@@ -188,7 +176,6 @@ port_92_close(void *priv)
free(dev);
}
void *
port_92_init(const device_t *info)
{
@@ -199,7 +186,7 @@ port_92_init(const device_t *info)
timer_add(&dev->pulse_timer, port_92_pulse, dev, 0);
dev->reg = 0;
dev->reg = 0;
mem_a20_alt = 0;
mem_a20_recalc();
@@ -209,7 +196,7 @@ port_92_init(const device_t *info)
port_92_add(dev);
dev->pulse_period = (uint64_t) (4.0 * SYSCLK * (double)(1ULL << 32ULL));
dev->pulse_period = (uint64_t) (4.0 * SYSCLK * (double) (1ULL << 32ULL));
dev->flags |= (PORT_92_RESET | PORT_92_A20);
@@ -217,57 +204,57 @@ port_92_init(const device_t *info)
}
const device_t port_92_device = {
.name = "Port 92 Register",
.name = "Port 92 Register",
.internal_name = "port_92",
.flags = 0,
.local = 0,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
.flags = 0,
.local = 0,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};
const device_t port_92_inv_device = {
.name = "Port 92 Register (inverted bits 2-7)",
.name = "Port 92 Register (inverted bits 2-7)",
.internal_name = "port_92_inv",
.flags = 0,
.local = PORT_92_INV,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
.flags = 0,
.local = PORT_92_INV,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};
const device_t port_92_word_device = {
.name = "Port 92 Register (16-bit)",
.name = "Port 92 Register (16-bit)",
.internal_name = "port_92_word",
.flags = 0,
.local = PORT_92_WORD,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
.flags = 0,
.local = PORT_92_WORD,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};
const device_t port_92_pci_device = {
.name = "Port 92 Register (PCI)",
.name = "Port 92 Register (PCI)",
.internal_name = "port_92_pci",
.flags = 0,
.local = PORT_92_PCI,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
.flags = 0,
.local = PORT_92_PCI,
.init = port_92_init,
.close = port_92_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};