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PIIX IDE non-bus master BAR's are now only writable on the SMSC Victory/66.

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This commit is contained in:
OBattler
2021-07-26 05:02:40 +02:00
parent 7eded88333
commit e864aa2edc
1 changed files with 32 additions and 16 deletions
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48
src/chipset/intel_piix.c
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@@ -613,36 +613,52 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[0x0d] = val & 0xf0;
break;
case 0x10:
fregs[0x10] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x10] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x11:
fregs[0x11] = val;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x11] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x14:
fregs[0x14] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x14] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x15:
fregs[0x15] = val;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x15] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x18:
fregs[0x18] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x18] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x19:
fregs[0x19] = val;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x19] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1c:
fregs[0x1c] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x1c] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1d:
fregs[0x1d] = val;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x1d] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x20:
fregs[0x20] = (val & 0xf0) | 1;