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Merge branch '86Box:master' into ps1-audio

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This commit is contained in:
Jasmine Iwanek
2022-01-29 17:11:20 -05:00
committed by GitHub
parent d8761e869a 0545de2570
commit f19510fd31
30 changed files with 1363 additions and 418 deletions
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127
.github/workflows/cmake.yml vendored
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@@ -83,53 +83,97 @@ jobs:
run: cmake --build build --target ${{ matrix.build.target }}
- uses: actions/upload-artifact@v2
with:
name: '86Box-${{ matrix.build.name }}-MSYS2-${{ matrix.environment.msystem }}-${{ github.sha }}'
name: '86Box-${{ matrix.build.name }}-MSYS2-${{ matrix.environment.msystem }}-gha${{ github.run_number }}'
path: build/artifacts/**
vs2019:
name: VS2019 ${{ matrix.build.name }} ${{ matrix.target-arch }} build (${{ matrix.toolset }})
llvm-windows:
name: "Windows vcpkg/LLVM (${{ matrix.build.name }} ${{ matrix.target.name }})"
runs-on: windows-latest
runs-on: windows-2022
env:
VCPKG_BINARY_SOURCES: 'clear;nuget,GitHub,readwrite'
strategy:
fail-fast: false
matrix:
build:
- name: Debug
dev-build: off
- name: Regular ODR
type: Release
new-dynarec: off
strip: --strip
- name: Debug ODR
slug: -Debug
type: Debug
- name: Dev
dev-build: on
new-dynarec: off
- name: Regular NDR
slug: -NDR
type: Release
strip: --strip
new-dynarec: on
- name: Debug NDR
slug: -NDR-Debug
type: Debug
target-arch: ['Win32', 'x64', 'ARM64']
toolset: ['clangcl']
new-dynarec: on
target:
- name: x86
triplet: x86-windows-static
toolchain: cmake/llvm-win32-i686.cmake
vcvars: x64_x86
- name: x64
triplet: x64-windows-static
toolchain: cmake/llvm-win32-x86_64.cmake
vcvars: x64
- name: ARM64
triplet: arm64-windows-static
toolchain: cmake/llvm-win32-aarch64.cmake
vcvars: x64_arm64
exclude:
- target-arch: 'ARM64'
build:
new-dynarec: off
- build:
new-dynarec: off
target:
name: ARM64
steps:
- uses: actions/checkout@v2
- uses: actions/cache@v2
with:
path: build/vcpkg_installed
key: vcpkg-${{ hashFiles('vcpkg.json') }}-${{ matrix.target-arch }}
- name: Download Ninja
run: >
Invoke-WebRequest https://github.com/ninja-build/ninja/releases/download/v1.10.2/ninja-win.zip -OutFile ninja-win.zip &&
Expand-Archive ninja-win.zip -DestinationPath .
- name: Setup NuGet Credentials
run: >
& (C:/vcpkg/vcpkg fetch nuget | tail -n 2)
sources add
-source "https://nuget.pkg.github.com/86Box/index.json"
-storepasswordincleartext
-name "GitHub"
-username "86Box"
-password "${{ secrets.GITHUB_TOKEN }}"
- name: vcpkg package restore
if: false
run: vcpkg install freetype libpng openal-soft sdl2 rtmidi --triplet ${{ matrix.target.triplet }}
- name: Configure CMake
run: >-
cmake -S . -B build
-G "Visual Studio 16 2019" -A ${{ matrix.target-arch }} -T ${{ matrix.toolset }}
-D CMAKE_TOOLCHAIN_FILE=C:\vcpkg\scripts\buildsystems\vcpkg.cmake
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D DEV_BRANCH=${{ matrix.build.dev-build }}
run: >
call "C:/Program Files/Microsoft Visual Studio/2022/Enterprise/VC/Auxiliary/Build/vcvarsall.bat" ${{ matrix.target.vcvars }}
set PATH=C:/Program Files/LLVM/bin;%PATH%
cmake -S . -B build -G Ninja -D CMAKE_BUILD_TYPE=${{ matrix.build.type }}
-D NEW_DYNAREC=${{ matrix.build.new-dynarec }}
-D VNC=OFF
-D CMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake
-D VCPKG_CHAINLOAD_TOOLCHAIN_FILE=${{ github.workspace }}/${{ matrix.target.toolchain }}
-D VCPKG_TARGET_TRIPLET=${{ matrix.target.triplet }}
shell: cmd
- name: Build
run: cmake --build build --config ${{ matrix.build.type }} --target install
run: |
call "C:/Program Files/Microsoft Visual Studio/2022/Enterprise/VC/Auxiliary/Build/vcvarsall.bat" ${{ matrix.target.vcvars }}
cmake --build build
shell: cmd
- name: Generate package
run: cmake --install build --prefix ./build/artifacts ${{ matrix.build.strip }}
- uses: actions/upload-artifact@v2
with:
name: '86Box-${{ matrix.build.name }}-VS2019-${{ matrix.target-arch }}-${{ matrix.toolset }}-${{ github.sha }}'
name: '86Box${{ matrix.build.slug }}-Windows-LLVM-${{ matrix.target.name }}-gha${{ github.run_number }}'
path: build/artifacts/**
linux:
@@ -166,21 +210,30 @@ jobs:
run: cmake --build build --target install
macos:
name: "macOS 11"
name: "macOS 11 (${{ matrix.build.name }} x86_64)"
runs-on: macos-11
strategy:
fail-fast: false
matrix:
build:
- name: Debug
dev-build: off
- name: Regular ODR
type: Release
new-dynarec: off
strip: --strip
- name: Debug ODR
slug: -Debug
type: Debug
- name: Dev
dev-build: on
new-dynarec: off
- name: Regular NDR
slug: -NDR
type: Release
strip: --strip
new-dynarec: on
- name: Debug NDR
slug: -NDR-Debug
type: Debug
new-dynarec: on
steps:
- uses: actions/checkout@v2
@@ -189,10 +242,14 @@ jobs:
- name: Configure CMake
run: >-
cmake -S . -B build
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D DEV_BRANCH=${{ matrix.build.dev-build }}
--toolchain cmake/flags-gcc-x86_64.cmake
-D NEW_DYNAREC=${{ matrix.build.new-dynarec }}
-D VNC=OFF
-D CMAKE_BUILD_TYPE=${{ matrix.build.type }}
- name: Build
run: cmake --build build --target install
run: cmake --build build
- name: Generate package
run: cmake --install build --prefix ./build/artifacts ${{ matrix.build.strip }}
- uses: actions/upload-artifact@v2
with:
name: '86Box${{ matrix.build.slug }}-macOS-x86_64-gha${{ github.run_number }}'
path: build/artifacts/**

1
CMakeLists.txt
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@@ -130,6 +130,7 @@ cmake_dependent_option(VNC "VNC renderer"
cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_RAMPAGE "AST Rampage" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_IAB "Intel Above Board" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_BRAT "BocaRAM/AT" ON "DEV_BRANCH" OFF)
# Determine the build type
set(RELEASE_BUILD OFF)

8
src/86box.c
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@@ -1046,8 +1046,12 @@ pc_reset_hard_init(void)
atfullspeed = 0;
pc_full_speed();
cycles = cycles_main = 0;
cycles = 0;
fpu_cycles = 0;
#ifdef USE_DYNAREC
cycles_main = 0;
#endif
update_mouse_msg();
}

15
src/cpu/386.c
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@@ -81,7 +81,20 @@ x386_log(const char *fmt, ...)
#define OP_TABLE(name) ops_ ## name
#define CLOCK_CYCLES(c) cycles -= (c)
#define CLOCK_CYCLES(c) \
{\
if (fpu_cycles > 0) {\
fpu_cycles -= (c);\
if (fpu_cycles < 0) {\
cycles += fpu_cycles;\
}\
} else {\
cycles -= (c);\
}\
}
#define CLOCK_CYCLES_FPU(c) cycles -= (c)
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
#include "x86_ops.h"

15
src/cpu/386_dynarec.c
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@@ -267,9 +267,22 @@ static void prefetch_flush()
#define OP_TABLE(name) ops_ ## name
#define CLOCK_CYCLES(c) cycles -= (c)
#define CLOCK_CYCLES(c) \
{\
if (fpu_cycles > 0) {\
fpu_cycles -= (c);\
if (fpu_cycles < 0) {\
cycles += fpu_cycles;\
}\
} else {\
cycles -= (c);\
}\
}
#define CLOCK_CYCLES_FPU(c) cycles -= (c)
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
#include "386_ops.h"

2
src/cpu/386_dynarec_ops.c
View File

@@ -65,6 +65,8 @@ static __inline void fetch_ea_16_long(uint32_t rmdat)
#define OP_TABLE(name) dynarec_ops_ ## name
#define CLOCK_CYCLES(c)
#define CLOCK_CYCLES_FPU(c)
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
#include "386_ops.h"

23
src/cpu/808x.c
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@@ -89,11 +89,32 @@ static int refresh = 0, cycdiff;
wait(val, 0); \
}
#define CLOCK_CYCLES(val) \
#define CLOCK_CYCLES_ALWAYS(val) \
{ \
wait(val, 0); \
}
#define CLOCK_CYCLES_FPU(val) \
{ \
wait(val, 0); \
}
#define CLOCK_CYCLES(val) \
{ \
if (fpu_cycles > 0) { \
fpu_cycles -= (val); \
if (fpu_cycles < 0) { \
wait(val, 0); \
} \
} else { \
wait(val, 0); \
} \
}
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
typedef int (*OpFn)(uint32_t fetchdat);

11
src/cpu/CMakeLists.txt
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@@ -13,8 +13,13 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(cpu OBJECT cpu.c cpu_table.c fpu.c x86.c 808x.c 386.c 386_common.c 386_dynarec.c
386_dynarec_ops.c x86seg.c x87.c x87_timings.c)
set(cpu_SOURCES cpu.c cpu_table.c fpu.c x86.c 808x.c 386.c 386_common.c 386_dynarec.c x86seg.c x87.c x87_timings.c)
if (DYNAREC)
set(cpu_SOURCES ${cpu_SOURCES} 386_dynarec_ops.c)
endif()
add_library(cpu OBJECT ${cpu_SOURCES})
if(AMD_K5)
target_compile_definitions(cpu PRIVATE USE_AMD_K5)
@@ -29,4 +34,4 @@ if(DYNAREC)
codegen_timing_common.c codegen_timing_k6.c
codegen_timing_pentium.c codegen_timing_p6.c
codegen_timing_winchip.c codegen_timing_winchip2.c)
endif()
endif()

1
src/cpu/cpu.c
View File

@@ -1369,6 +1369,7 @@ cpu_set(void)
case FPU_487SX:
default:
x87_timings = x87_timings_486;
x87_concurrency = x87_concurrency_486;
}
if (is386) {

3
src/cpu/cpu.h
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@@ -354,7 +354,7 @@ typedef struct {
uint8_t ssegs, ismmx,
abrt, _smi_line;
int _cycles, _in_smm;
int _cycles, _fpu_cycles, _in_smm;
uint16_t npxs, npxc;
@@ -457,6 +457,7 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
#define DI cpu_state.regs[7].w
#define cycles cpu_state._cycles
#define fpu_cycles cpu_state._fpu_cycles
#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm
#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod

4
src/cpu/x86seg.c
View File

@@ -2415,7 +2415,9 @@ cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg)
cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATDS;
#ifdef USE_DYNAREC
codegen_flat_ds = 0;
#endif
}
if (seg == &cpu_state.seg_ss) {
if (seg->base == 0 && seg->limit_low == 0 && seg->limit_high == 0xffffffff)
@@ -2423,7 +2425,9 @@ cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg)
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
set_stack32((segdat[3] & 0x40) ? 1 : 0);
#ifdef USE_DYNAREC
codegen_flat_ss = 0;
#endif
}
}
}

108
src/cpu/x87_ops_arith.h
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@@ -12,7 +12,8 @@ static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
if ((cpu_state.npxc >> 10) & 3) \
fesetround(FE_TONEAREST); \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd ## cycle_postfix) : ((x87_concurrency.fadd ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -24,7 +25,8 @@ static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
cpu_state.npxs &= ~(C0|C2|C3); \
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom ## cycle_postfix) : ((x87_timings.fcom ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom ## cycle_postfix) : ((x87_timings.fcom ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom ## cycle_postfix) : ((x87_concurrency.fcom ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -37,7 +39,8 @@ static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat) \
cpu_state.npxs &= ~(C0|C2|C3); \
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
x87_pop(); \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom ## cycle_postfix) : ((x87_timings.fcom ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom ## cycle_postfix) : ((x87_timings.fcom ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom ## cycle_postfix) : ((x87_concurrency.fcom ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -49,7 +52,8 @@ static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
x87_div(ST(0), ST(0), use_var); \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv ## cycle_postfix) : ((x87_timings.fdiv ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv ## cycle_postfix) : ((x87_timings.fdiv ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd ## cycle_postfix) : ((x87_concurrency.fadd ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -61,7 +65,8 @@ static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
x87_div(ST(0), use_var, ST(0)); \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv ## cycle_postfix) : ((x87_timings.fdiv ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv ## cycle_postfix) : ((x87_timings.fdiv ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv ## cycle_postfix) : ((x87_concurrency.fdiv ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -73,7 +78,8 @@ static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
ST(0) *= use_var; \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fmul ## cycle_postfix) : ((x87_timings.fmul ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fmul ## cycle_postfix) : ((x87_timings.fmul ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fmul ## cycle_postfix) : ((x87_concurrency.fmul ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -85,7 +91,8 @@ static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
ST(0) -= use_var; \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd ## cycle_postfix) : ((x87_concurrency.fadd ## cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat) \
@@ -97,7 +104,8 @@ static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat) \
load_var = get(); if (cpu_state.abrt) return 1; \
ST(0) = use_var - ST(0); \
FP_TAG_VALID; \
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd ## cycle_postfix) : ((x87_timings.fadd ## cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd ## cycle_postfix) : ((x87_concurrency.fadd ## cycle_postfix) * cpu_multi)); \
return 0; \
}
@@ -127,7 +135,8 @@ static int opFADD(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = ST(0) + ST(fetchdat & 7);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFADDr(uint32_t fetchdat)
@@ -136,7 +145,8 @@ static int opFADDr(uint32_t fetchdat)
cpu_state.pc++;
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFADDP(uint32_t fetchdat)
@@ -146,7 +156,8 @@ static int opFADDP(uint32_t fetchdat)
ST(fetchdat & 7) = ST(fetchdat & 7) + ST(0);
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
@@ -157,7 +168,8 @@ static int opFCOM(uint32_t fetchdat)
cpu_state.npxs &= ~(C0|C2|C3);
if (ST(0) == ST(fetchdat & 7)) cpu_state.npxs |= C3;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.npxs |= C0;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
@@ -168,7 +180,8 @@ static int opFCOMP(uint32_t fetchdat)
cpu_state.npxs &= ~(C0|C2|C3);
cpu_state.npxs |= x87_compare(ST(0), ST(fetchdat & 7));
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
@@ -187,7 +200,8 @@ static int opFCOMPP(uint32_t fetchdat)
x87_pop();
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -199,7 +213,8 @@ static int opFUCOMPP(uint32_t fetchdat)
cpu_state.npxs |= x87_ucompare(ST(0), ST(1));
x87_pop();
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
@@ -211,7 +226,8 @@ static int opFCOMI(uint32_t fetchdat)
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
static int opFCOMIP(uint32_t fetchdat)
@@ -223,7 +239,8 @@ static int opFCOMIP(uint32_t fetchdat)
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom) : (x87_timings.fcom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
#endif
@@ -234,7 +251,8 @@ static int opFDIV(uint32_t fetchdat)
cpu_state.pc++;
x87_div(ST(0), ST(0), ST(fetchdat & 7));
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
static int opFDIVr(uint32_t fetchdat)
@@ -243,7 +261,8 @@ static int opFDIVr(uint32_t fetchdat)
cpu_state.pc++;
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
static int opFDIVP(uint32_t fetchdat)
@@ -253,7 +272,8 @@ static int opFDIVP(uint32_t fetchdat)
x87_div(ST(fetchdat & 7), ST(fetchdat & 7), ST(0));
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
@@ -263,7 +283,8 @@ static int opFDIVR(uint32_t fetchdat)
cpu_state.pc++;
x87_div(ST(0), ST(fetchdat&7), ST(0));
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
static int opFDIVRr(uint32_t fetchdat)
@@ -272,7 +293,8 @@ static int opFDIVRr(uint32_t fetchdat)
cpu_state.pc++;
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
static int opFDIVRP(uint32_t fetchdat)
@@ -282,7 +304,8 @@ static int opFDIVRP(uint32_t fetchdat)
x87_div(ST(fetchdat & 7), ST(0), ST(fetchdat & 7));
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv) : (x87_timings.fdiv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv) : (x87_concurrency.fdiv * cpu_multi));
return 0;
}
@@ -292,7 +315,8 @@ static int opFMUL(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = ST(0) * ST(fetchdat & 7);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fmul) : (x87_concurrency.fmul * cpu_multi));
return 0;
}
static int opFMULr(uint32_t fetchdat)
@@ -301,7 +325,8 @@ static int opFMULr(uint32_t fetchdat)
cpu_state.pc++;
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fmul) : (x87_concurrency.fmul * cpu_multi));
return 0;
}
static int opFMULP(uint32_t fetchdat)
@@ -311,7 +336,8 @@ static int opFMULP(uint32_t fetchdat)
ST(fetchdat & 7) = ST(0) * ST(fetchdat & 7);
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fmul) : (x87_timings.fmul * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fmul) : (x87_concurrency.fmul * cpu_multi));
return 0;
}
@@ -321,7 +347,8 @@ static int opFSUB(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = ST(0) - ST(fetchdat & 7);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFSUBr(uint32_t fetchdat)
@@ -330,7 +357,8 @@ static int opFSUBr(uint32_t fetchdat)
cpu_state.pc++;
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFSUBP(uint32_t fetchdat)
@@ -340,7 +368,8 @@ static int opFSUBP(uint32_t fetchdat)
ST(fetchdat & 7) = ST(fetchdat & 7) - ST(0);
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
@@ -350,7 +379,8 @@ static int opFSUBR(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = ST(fetchdat & 7) - ST(0);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFSUBRr(uint32_t fetchdat)
@@ -359,7 +389,8 @@ static int opFSUBRr(uint32_t fetchdat)
cpu_state.pc++;
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
FP_TAG_VALID_F;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
static int opFSUBRP(uint32_t fetchdat)
@@ -369,7 +400,8 @@ static int opFSUBRP(uint32_t fetchdat)
ST(fetchdat & 7) = ST(0) - ST(fetchdat & 7);
FP_TAG_VALID_F;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd) : (x87_timings.fadd * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd) : (x87_concurrency.fadd * cpu_multi));
return 0;
}
@@ -380,7 +412,8 @@ static int opFUCOM(uint32_t fetchdat)
cpu_state.pc++;
cpu_state.npxs &= ~(C0|C2|C3);
cpu_state.npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
@@ -391,7 +424,8 @@ static int opFUCOMP(uint32_t fetchdat)
cpu_state.npxs &= ~(C0|C2|C3);
cpu_state.npxs |= x87_ucompare(ST(0), ST(fetchdat & 7));
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
@@ -403,7 +437,8 @@ static int opFUCOMI(uint32_t fetchdat)
cpu_state.flags &= ~(Z_FLAG | P_FLAG | C_FLAG);
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
static int opFUCOMIP(uint32_t fetchdat)
@@ -415,7 +450,8 @@ static int opFUCOMIP(uint32_t fetchdat)
if (ST(0) == ST(fetchdat & 7)) cpu_state.flags |= Z_FLAG;
else if (ST(0) < ST(fetchdat & 7)) cpu_state.flags |= C_FLAG;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fucom) : (x87_timings.fucom * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
#endif

101
src/cpu/x87_ops_loadstore.h
View File

@@ -23,7 +23,8 @@ static int opFILDiw_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteaw(); if (cpu_state.abrt) return 1;
x87_push((double)temp);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_16) : (x87_timings.fild_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_16) : (x87_timings.fild_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_16) : (x87_concurrency.fild_16 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -35,7 +36,8 @@ static int opFILDiw_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteaw(); if (cpu_state.abrt) return 1;
x87_push((double)temp);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_16) : (x87_timings.fild_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_16) : (x87_timings.fild_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_16) : (x87_concurrency.fild_16 * cpu_multi));
return 0;
}
#endif
@@ -46,7 +48,8 @@ static int opFISTiw_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(x87_fround16(ST(0)));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_16) : (x87_concurrency.fist_16 * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -56,7 +59,8 @@ static int opFISTiw_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(x87_fround16(ST(0)));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_16) : (x87_concurrency.fist_16 * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -68,7 +72,8 @@ static int opFISTPiw_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(x87_fround16(ST(0))); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_16) : (x87_concurrency.fist_16 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -79,7 +84,8 @@ static int opFISTPiw_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(x87_fround16(ST(0))); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_16) : (x87_timings.fist_16 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_16) : (x87_concurrency.fist_16 * cpu_multi));
return 0;
}
#endif
@@ -95,7 +101,8 @@ static int opFILDiq_a16(uint32_t fetchdat)
cpu_state.MM[cpu_state.TOP&7].q = temp64;
FP_TAG_DEFAULT;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_64) : (x87_timings.fild_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_64) : (x87_timings.fild_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_64) : (x87_concurrency.fild_64 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -110,7 +117,8 @@ static int opFILDiq_a32(uint32_t fetchdat)
cpu_state.MM[cpu_state.TOP&7].q = temp64;
FP_TAG_DEFAULT;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_64) : (x87_timings.fild_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_64) : (x87_timings.fild_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_64) : (x87_concurrency.fild_64 * cpu_multi));
return 0;
}
#endif
@@ -139,7 +147,8 @@ static int FBSTP_a16(uint32_t fetchdat)
if (ST(0) < 0.0) tempc |= 0x80;
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fbstp) : (x87_timings.fbstp * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fbstp) : (x87_timings.fbstp * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fbstp) : (x87_concurrency.fbstp * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -167,7 +176,7 @@ static int FBSTP_a32(uint32_t fetchdat)
if (ST(0) < 0.0) tempc |= 0x80;
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fbstp) : (x87_timings.fbstp * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fbstp) : (x87_timings.fbstp * cpu_multi));
return 0;
}
#endif
@@ -184,7 +193,8 @@ static int FISTPiq_a16(uint32_t fetchdat)
temp64 = x87_fround(ST(0));
seteaq(temp64); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_64) : (x87_timings.fist_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_64) : (x87_timings.fist_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_64) : (x87_concurrency.fist_64 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -200,7 +210,8 @@ static int FISTPiq_a32(uint32_t fetchdat)
temp64 = x87_fround(ST(0));
seteaq(temp64); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_64) : (x87_timings.fist_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_64) : (x87_timings.fist_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_64) : (x87_concurrency.fist_64 * cpu_multi));
return 0;
}
#endif
@@ -213,7 +224,8 @@ static int opFILDil_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
templ = geteal(); if (cpu_state.abrt) return 1;
x87_push((double)templ);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_32) : (x87_timings.fild_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_32) : (x87_timings.fild_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_32) : (x87_concurrency.fild_32 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -225,7 +237,8 @@ static int opFILDil_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
templ = geteal(); if (cpu_state.abrt) return 1;
x87_push((double)templ);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fild_32) : (x87_timings.fild_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fild_32) : (x87_timings.fild_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fild_32) : (x87_concurrency.fild_32 * cpu_multi));
return 0;
}
#endif
@@ -236,7 +249,8 @@ static int opFISTil_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(x87_fround32(ST(0)));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_32) : (x87_concurrency.fist_32 * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -246,7 +260,8 @@ static int opFISTil_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(x87_fround32(ST(0)));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_32) : (x87_concurrency.fist_32 * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -258,7 +273,8 @@ static int opFISTPil_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(x87_fround32(ST(0))); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_32) : (x87_concurrency.fist_32 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -269,7 +285,8 @@ static int opFISTPil_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteal(x87_fround32(ST(0))); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fist_32) : (x87_timings.fist_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fist_32) : (x87_concurrency.fist_32 * cpu_multi));
return 0;
}
#endif
@@ -282,7 +299,8 @@ static int opFLDe_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
t=x87_ld80(); if (cpu_state.abrt) return 1;
x87_push(t);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_80) : (x87_concurrency.fld_80 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -294,7 +312,8 @@ static int opFLDe_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
t=x87_ld80(); if (cpu_state.abrt) return 1;
x87_push(t);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_80) : (x87_concurrency.fld_80 * cpu_multi));
return 0;
}
#endif
@@ -306,7 +325,8 @@ static int opFSTPe_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_80) : (x87_concurrency.fld_80 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -317,7 +337,8 @@ static int opFSTPe_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
x87_st80(ST(0)); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_80) : (x87_timings.fld_80 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_80) : (x87_concurrency.fld_80 * cpu_multi));
return 0;
}
#endif
@@ -330,7 +351,8 @@ static int opFLDd_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
t.i = geteaq(); if (cpu_state.abrt) return 1;
x87_push(t.d);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_64) : (x87_timings.fld_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_64) : (x87_timings.fld_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_64) : (x87_concurrency.fld_64 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -342,7 +364,8 @@ static int opFLDd_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
t.i = geteaq(); if (cpu_state.abrt) return 1;
x87_push(t.d);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_64) : (x87_timings.fld_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_64) : (x87_timings.fld_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_64) : (x87_concurrency.fld_64 * cpu_multi));
return 0;
}
#endif
@@ -355,7 +378,8 @@ static int opFSTd_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
t.d = ST(0);
seteaq(t.i);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_64) : (x87_concurrency.fst_64 * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -367,7 +391,8 @@ static int opFSTd_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
t.d = ST(0);
seteaq(t.i);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_64) : (x87_concurrency.fst_64 * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -381,7 +406,8 @@ static int opFSTPd_a16(uint32_t fetchdat)
t.d = ST(0);
seteaq(t.i); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_64) : (x87_concurrency.fst_64 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -394,7 +420,8 @@ static int opFSTPd_a32(uint32_t fetchdat)
t.d = ST(0);
seteaq(t.i); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_64) : (x87_timings.fst_64 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_64) : (x87_concurrency.fst_64 * cpu_multi));
return 0;
}
#endif
@@ -407,7 +434,8 @@ static int opFLDs_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
ts.i = geteal(); if (cpu_state.abrt) return 1;
x87_push((double)ts.s);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -419,7 +447,8 @@ static int opFLDs_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
ts.i = geteal(); if (cpu_state.abrt) return 1;
x87_push((double)ts.s);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return 0;
}
#endif
@@ -432,7 +461,8 @@ static int opFSTs_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
ts.s = (float)ST(0);
seteal(ts.i);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -444,7 +474,8 @@ static int opFSTs_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
ts.s = (float)ST(0);
seteal(ts.i);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -458,7 +489,8 @@ static int opFSTPs_a16(uint32_t fetchdat)
ts.s = (float)ST(0);
seteal(ts.i); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -471,7 +503,8 @@ static int opFSTPs_a32(uint32_t fetchdat)
ts.s = (float)ST(0);
seteal(ts.i); if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst_32) : (x87_timings.fst_32 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst_32) : (x87_concurrency.fst_32 * cpu_multi));
return 0;
}
#endif

140
src/cpu/x87_ops_misc.h
View File

@@ -15,7 +15,8 @@ static int opFSTSW_AX(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
AX = cpu_state.npxs;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
return 0;
}
#endif
@@ -25,7 +26,8 @@ static int opFNOP(uint32_t fetchdat)
{
FP_ENTER();
cpu_state.pc++;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fnop) : (x87_concurrency.fnop * cpu_multi));
return 0;
}
@@ -34,7 +36,8 @@ static int opFCLEX(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
cpu_state.npxs &= 0xff00;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fnop) : (x87_concurrency.fnop * cpu_multi));
return 0;
}
@@ -58,7 +61,8 @@ static int opFINIT(uint32_t fetchdat)
#endif
cpu_state.TOP = 0;
cpu_state.ismmx = 0;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.finit) : (x87_timings.finit * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.finit) : (x87_timings.finit * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.finit) : (x87_concurrency.finit * cpu_multi));
CPU_BLOCK_END();
return 0;
}
@@ -73,7 +77,8 @@ static int opFFREE(uint32_t fetchdat)
#else
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = 3;
#endif
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.ffree) : (x87_timings.ffree * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.ffree) : (x87_timings.ffree * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.ffree) : (x87_concurrency.ffree * cpu_multi));
return 0;
}
@@ -83,7 +88,8 @@ static int opFFREEP(uint32_t fetchdat)
cpu_state.pc++;
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = 3; if (cpu_state.abrt) return 1;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.ffree) : (x87_timings.ffree * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.ffree) : (x87_timings.ffree * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.ffree) : (x87_concurrency.ffree * cpu_multi));
return 0;
}
@@ -93,7 +99,8 @@ static int opFST(uint32_t fetchdat)
cpu_state.pc++;
ST(fetchdat & 7) = ST(0);
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst) : (x87_timings.fst * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst) : (x87_timings.fst * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst) : (x87_concurrency.fst * cpu_multi));
return 0;
}
@@ -104,7 +111,8 @@ static int opFSTP(uint32_t fetchdat)
ST(fetchdat & 7) = ST(0);
cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = cpu_state.tag[cpu_state.TOP & 7];
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fst) : (x87_timings.fst * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fst) : (x87_timings.fst * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fst) : (x87_concurrency.fst * cpu_multi));
return 0;
}
@@ -160,7 +168,8 @@ static int FSTOR()
#endif
cpu_state.ismmx = 1;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.frstor) : (x87_concurrency.frstor * cpu_multi));
return cpu_state.abrt;
}
static int opFSTOR_a16(uint32_t fetchdat)
@@ -330,7 +339,8 @@ static int FSAVE()
cpu_state.TOP = 0;
cpu_state.ismmx = 0;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsave) : (x87_concurrency.fsave * cpu_multi));
return cpu_state.abrt;
}
static int opFSAVE_a16(uint32_t fetchdat)
@@ -358,7 +368,8 @@ static int opFSTSW_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw((cpu_state.npxs & 0xC7FF) | ((cpu_state.TOP & 7) << 11));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -368,7 +379,8 @@ static int opFSTSW_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw((cpu_state.npxs & 0xC7FF) | ((cpu_state.TOP & 7) << 11));
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -386,7 +398,8 @@ static int opFLD(uint32_t fetchdat)
x87_push(ST(fetchdat&7));
cpu_state.tag[cpu_state.TOP&7] = old_tag;
cpu_state.MM[cpu_state.TOP&7].q = old_i64;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld) : (x87_timings.fld * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld) : (x87_timings.fld * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld) : (x87_concurrency.fld * cpu_multi));
return 0;
}
@@ -407,7 +420,8 @@ static int opFXCH(uint32_t fetchdat)
cpu_state.MM[cpu_state.TOP&7].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q;
cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q = old_i64;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fxch) : (x87_timings.fxch * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fxch) : (x87_timings.fxch * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fxch) : (x87_concurrency.fxch * cpu_multi));
return 0;
}
@@ -417,7 +431,8 @@ static int opFCHS(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = -ST(0);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fchs) : (x87_timings.fchs * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fchs) : (x87_timings.fchs * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fchs) : (x87_concurrency.fchs * cpu_multi));
return 0;
}
@@ -427,7 +442,8 @@ static int opFABS(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = fabs(ST(0));
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fabs) : (x87_timings.fabs * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fabs) : (x87_timings.fabs * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fabs) : (x87_concurrency.fabs * cpu_multi));
return 0;
}
@@ -438,7 +454,8 @@ static int opFTST(uint32_t fetchdat)
cpu_state.npxs &= ~(C0|C2|C3);
if (ST(0) == 0.0) cpu_state.npxs |= C3;
else if (ST(0) < 0.0) cpu_state.npxs |= C0;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.ftst) : (x87_timings.ftst * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.ftst) : (x87_timings.ftst * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.ftst) : (x87_concurrency.ftst * cpu_multi));
return 0;
}
@@ -455,7 +472,8 @@ static int opFXAM(uint32_t fetchdat)
else if (ST(0) == 0.0) cpu_state.npxs |= C3;
else cpu_state.npxs |= C2;
if (ST(0) < 0.0) cpu_state.npxs |= C1;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fxam) : (x87_timings.fxam * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fxam) : (x87_timings.fxam * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fxam) : (x87_concurrency.fxam * cpu_multi));
return 0;
}
@@ -464,7 +482,8 @@ static int opFLD1(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push(1.0);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_z1) : (x87_timings.fld_z1 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_z1) : (x87_timings.fld_z1 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_z1) : (x87_concurrency.fld_z1 * cpu_multi));
return 0;
}
@@ -473,7 +492,8 @@ static int opFLDL2T(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push(3.3219280948873623);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));
return 0;
}
@@ -482,7 +502,8 @@ static int opFLDL2E(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push(1.4426950408889634);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));
return 0;
}
@@ -491,7 +512,8 @@ static int opFLDPI(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push(3.141592653589793);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));
return 0;
}
@@ -500,7 +522,8 @@ static int opFLDEG2(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push(0.3010299956639812);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));
return 0;
}
@@ -509,7 +532,8 @@ static int opFLDLN2(uint32_t fetchdat)
FP_ENTER();
cpu_state.pc++;
x87_push_u64(0x3fe62e42fefa39f0ull);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));
return 0;
}
@@ -519,7 +543,8 @@ static int opFLDZ(uint32_t fetchdat)
cpu_state.pc++;
x87_push(0.0);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fld_z1) : (x87_timings.fld_z1 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_z1) : (x87_timings.fld_z1 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_z1) : (x87_concurrency.fld_z1 * cpu_multi));
return 0;
}
@@ -529,7 +554,8 @@ static int opF2XM1(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = pow(2.0, ST(0)) - 1.0;
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.f2xm1) : (x87_timings.f2xm1 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.f2xm1) : (x87_timings.f2xm1 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.f2xm1) : (x87_concurrency.f2xm1 * cpu_multi));
return 0;
}
@@ -540,7 +566,8 @@ static int opFYL2X(uint32_t fetchdat)
ST(1) = ST(1) * (log(ST(0)) / log(2.0));
FP_TAG_VALID_N;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fyl2x) : (x87_timings.fyl2x * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fyl2x) : (x87_timings.fyl2x * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fyl2x) : (x87_concurrency.fyl2x * cpu_multi));
return 0;
}
@@ -551,7 +578,8 @@ static int opFYL2XP1(uint32_t fetchdat)
ST(1) = ST(1) * (log1p(ST(0)) / log(2.0));
FP_TAG_VALID_N;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fyl2xp1) : (x87_timings.fyl2xp1 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fyl2xp1) : (x87_timings.fyl2xp1 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fyl2xp1) : (x87_concurrency.fyl2xp1 * cpu_multi));
return 0;
}
@@ -563,7 +591,8 @@ static int opFPTAN(uint32_t fetchdat)
FP_TAG_VALID;
x87_push(1.0);
cpu_state.npxs &= ~C2;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fptan) : (x87_timings.fptan * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fptan) : (x87_timings.fptan * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fptan) : (x87_concurrency.fptan * cpu_multi));
return 0;
}
@@ -574,7 +603,8 @@ static int opFPATAN(uint32_t fetchdat)
ST(1) = atan2(ST(1), ST(0));
FP_TAG_VALID_N;
x87_pop();
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fpatan) : (x87_timings.fpatan * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fpatan) : (x87_timings.fpatan * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fpatan) : (x87_concurrency.fpatan * cpu_multi));
return 0;
}
@@ -587,7 +617,8 @@ static int opFDECSTP(uint32_t fetchdat)
#else
cpu_state.TOP = (cpu_state.TOP - 1) & 7;
#endif
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fincdecstp) : (x87_timings.fincdecstp * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fincdecstp) : (x87_timings.fincdecstp * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fincdecstp) : (x87_concurrency.fincdecstp * cpu_multi));
return 0;
}
@@ -600,7 +631,8 @@ static int opFINCSTP(uint32_t fetchdat)
#else
cpu_state.TOP = (cpu_state.TOP + 1) & 7;
#endif
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fincdecstp) : (x87_timings.fincdecstp * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fincdecstp) : (x87_timings.fincdecstp * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fincdecstp) : (x87_concurrency.fincdecstp * cpu_multi));
return 0;
}
@@ -616,7 +648,8 @@ static int opFPREM(uint32_t fetchdat)
if (temp64 & 4) cpu_state.npxs|=C0;
if (temp64 & 2) cpu_state.npxs|=C3;
if (temp64 & 1) cpu_state.npxs|=C1;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fprem) : (x87_timings.fprem * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fprem) : (x87_timings.fprem * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fprem) : (x87_concurrency.fprem * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -632,7 +665,8 @@ static int opFPREM1(uint32_t fetchdat)
if (temp64 & 4) cpu_state.npxs|=C0;
if (temp64 & 2) cpu_state.npxs|=C3;
if (temp64 & 1) cpu_state.npxs|=C1;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fprem1) : (x87_timings.fprem1 * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fprem1) : (x87_timings.fprem1 * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fprem1) : (x87_concurrency.fprem1 * cpu_multi));
return 0;
}
#endif
@@ -643,7 +677,8 @@ static int opFSQRT(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = sqrt(ST(0));
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fsqrt) : (x87_timings.fsqrt * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsqrt) : (x87_timings.fsqrt * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsqrt) : (x87_concurrency.fsqrt * cpu_multi));
return 0;
}
@@ -658,7 +693,8 @@ static int opFSINCOS(uint32_t fetchdat)
FP_TAG_VALID;
x87_push(cos(td));
cpu_state.npxs &= ~C2;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fsincos) : (x87_timings.fsincos * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsincos) : (x87_timings.fsincos * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsincos) : (x87_concurrency.fsincos * cpu_multi));
return 0;
}
#endif
@@ -669,7 +705,8 @@ static int opFRNDINT(uint32_t fetchdat)
cpu_state.pc++;
ST(0) = (double)x87_fround(ST(0));
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.frndint) : (x87_timings.frndint * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frndint) : (x87_timings.frndint * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.frndint) : (x87_concurrency.frndint * cpu_multi));
return 0;
}
@@ -682,7 +719,8 @@ static int opFSCALE(uint32_t fetchdat)
if(ST(0) != 0.0)
ST(0) = ST(0) * pow(2.0, (double)temp64);
FP_TAG_VALID;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fscale) : (x87_timings.fscale * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fscale) : (x87_timings.fscale * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fscale) : (x87_concurrency.fscale * cpu_multi));
return 0;
}
@@ -694,7 +732,8 @@ static int opFSIN(uint32_t fetchdat)
ST(0) = sin(ST(0));
FP_TAG_VALID;
cpu_state.npxs &= ~C2;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fsin_cos) : (x87_timings.fsin_cos * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsin_cos) : (x87_timings.fsin_cos * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsin_cos) : (x87_concurrency.fsin_cos * cpu_multi));
return 0;
}
@@ -705,7 +744,8 @@ static int opFCOS(uint32_t fetchdat)
ST(0) = cos(ST(0));
FP_TAG_VALID;
cpu_state.npxs &= ~C2;
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fsin_cos) : (x87_timings.fsin_cos * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsin_cos) : (x87_timings.fsin_cos * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsin_cos) : (x87_concurrency.fsin_cos * cpu_multi));
return 0;
}
#endif
@@ -733,7 +773,8 @@ static int FLDENV()
cpu_state.TOP = (cpu_state.npxs >> 11) & 7;
break;
}
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fldenv) : (x87_timings.fldenv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldenv) : (x87_timings.fldenv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldenv) : (x87_concurrency.fldenv * cpu_multi));
return cpu_state.abrt;
}
@@ -766,7 +807,8 @@ static int opFLDCW_a16(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.npxc = tempw;
codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldcw) : (x87_concurrency.fldcw * cpu_multi));
return 0;
}
#ifndef FPU_8087
@@ -780,7 +822,8 @@ static int opFLDCW_a32(uint32_t fetchdat)
if (cpu_state.abrt) return 1;
cpu_state.npxc = tempw;
codegen_set_rounding_mode((cpu_state.npxc >> 10) & 3);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldcw) : (x87_concurrency.fldcw * cpu_multi));
return 0;
}
#endif
@@ -826,7 +869,8 @@ static int FSTENV()
writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
break;
}
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
return cpu_state.abrt;
}
@@ -855,7 +899,8 @@ static int opFSTCW_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(cpu_state.npxc);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
return cpu_state.abrt;
}
#ifndef FPU_8087
@@ -865,7 +910,8 @@ static int opFSTCW_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
seteaw(cpu_state.npxc);
CLOCK_CYCLES((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
return cpu_state.abrt;
}
#endif
@@ -882,7 +928,7 @@ static int opFSTCW_a32(uint32_t fetchdat)
cpu_state.MM[cpu_state.TOP&7].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q; \
ST(0) = ST(fetchdat & 7); \
} \
CLOCK_CYCLES(4); \
CLOCK_CYCLES_FPU(4); \
return 0; \
}

155
src/cpu/x87_timings.c
View File

@@ -8,6 +8,7 @@
#include "x87_timings.h"
x87_timings_t x87_timings;
x87_timings_t x87_concurrency;
const x87_timings_t x87_timings_8087 =
{
@@ -313,3 +314,157 @@ const x87_timings_t x87_timings_486 =
.fyl2x = (196 + 329) / 2,
.fyl2xp1 = (171 + 326) / 2
};
/* this should be used for FPUs with no concurrency.
some pre-486DX Cyrix FPUs reportedly are like this. */
const x87_timings_t x87_concurrency_none =
{
.f2xm1 = 0,
.fabs = 0,
.fadd = 0,
.fadd_32 = 0,
.fadd_64 = 0,
.fbld = 0,
.fbstp = 0,
.fchs = 0,
.fclex = 0,
.fcom = 0,
.fcom_32 = 0,
.fcom_64 = 0,
.fcos = 0,
.fincdecstp = 0,
.fdisi_eni = 0,
.fdiv = 0,
.fdiv_32 = 0,
.fdiv_64 = 0,
.ffree = 0,
.fadd_i16 = 0,
.fadd_i32 = 0,
.fcom_i16 = 0,
.fcom_i32 = 0,
.fdiv_i16 = 0,
.fdiv_i32 = 0,
.fild_16 = 0,
.fild_32 = 0,
.fild_64 = 0,
.fmul_i16 = 0,
.fmul_i32 = 0,
.finit = 0,
.fist_16 = 0,
.fist_32 = 0,
.fist_64 = 0,
.fld = 0,
.fld_32 = 0,
.fld_64 = 0,
.fld_80 = 0,
.fld_z1 = 0,
.fld_const = 0,
.fldcw = 0,
.fldenv = 0,
.fmul = 0,
.fmul_32 = 0,
.fmul_64 = 0,
.fnop = 0,
.fpatan = 0,
.fprem = 0,
.fprem1 = 0,
.fptan = 0,
.frndint = 0,
.frstor = 0,
.fsave = 0,
.fscale = 0,
.fsetpm = 0,
.fsin_cos = 0,
.fsincos = 0,
.fsqrt = 0,
.fst = 0,
.fst_32 = 0,
.fst_64 = 0,
.fst_80 = 0,
.fstcw_sw = 0,
.fstenv = 0,
.ftst = 0,
.fucom = 0,
.fwait = 0,
.fxam = 0,
.fxch = 0,
.fxtract = 0,
.fyl2x = 0,
.fyl2xp1 = 0,
};
const x87_timings_t x87_concurrency_486 =
{
.f2xm1 = 2,
.fabs = 0,
.fadd = 7,
.fadd_32 = 7,
.fadd_64 = 7,
.fbld = 8,
.fbstp = 0,
.fchs = 0,
.fclex = 0,
.fcom = 1,
.fcom_32 = 1,
.fcom_64 = 1,
.fcos = 2,
.fincdecstp = 0,
.fdisi_eni = 0,
.fdiv = 70,
.fdiv_32 = 70,
.fdiv_64 = 70,
.ffree = 0,
.fadd_i16 = 7,
.fadd_i32 = 7,
.fcom_i16 = 1,
.fcom_i32 = 1,
.fdiv_i16 = 70,
.fdiv_i32 = 70,
.fild_16 = 4,
.fild_32 = 4,
.fild_64 = 8,
.fmul_i16 = 8,
.fmul_i32 = 8,
.finit = 0,
.fist_16 = 0,
.fist_32 = 0,
.fist_64 = 0,
.fld = 0,
.fld_32 = 0,
.fld_64 = 0,
.fld_80 = 0,
.fld_z1 = 0,
.fld_const = 2,
.fldcw = 0,
.fldenv = 0,
.fmul = 13,
.fmul_32 = 8,
.fmul_64 = 11,
.fnop = 0,
.fpatan = 5,
.fprem = 2,
.fprem1 = 6,
.fptan = 70,
.frndint = 0,
.frstor = 0,
.fsave = 0,
.fscale = 2,
.fsetpm = 0,
.fsin_cos = 2,
.fsincos = 2,
.fsqrt = 70,
.fst = 0,
.fst_32 = 0,
.fst_64 = 0,
.fst_80 = 0,
.fstcw_sw = 0,
.fstenv = 0,
.ftst = 1,
.fucom = 1,
.fwait = 0,
.fxam = 0,
.fxch = 0,
.fxtract = 4,
.fyl2x = 13,
.fyl2xp1 = 13,
};

5
src/cpu/x87_timings.h
View File

@@ -53,4 +53,7 @@ extern const x87_timings_t x87_timings_287;
extern const x87_timings_t x87_timings_387;
extern const x87_timings_t x87_timings_486;
extern x87_timings_t x87_timings;
extern const x87_timings_t x87_concurrency_486;
extern x87_timings_t x87_timings;
extern x87_timings_t x87_concurrency;

6
src/device/CMakeLists.txt
View File

@@ -29,4 +29,8 @@ endif()
if(ISAMEM_IAB)
target_compile_definitions(dev PRIVATE USE_ISAMEM_IAB)
endif()
endif()
if(ISAMEM_BRAT)
target_compile_definitions(dev PRIVATE USE_ISAMEM_BRAT)
endif()

92
src/device/isamem.c
View File

@@ -94,6 +94,7 @@
#define ISAMEM_EV159_CARD 10
#define ISAMEM_RAMPAGEXT_CARD 11
#define ISAMEM_ABOVEBOARD_CARD 12
#define ISAMEM_BRAT_CARD 13
#define ISAMEM_DEBUG 0
@@ -451,6 +452,7 @@ dev->frame_addr = 0xE0000;
case ISAMEM_RAMPAGEXT_CARD: /* AST RAMpage/XT */
case ISAMEM_ABOVEBOARD_CARD: /* Intel AboveBoard */
case ISAMEM_BRAT_CARD: /* BocaRAM/AT */
dev->base_addr = device_get_config_hex16("base");
dev->total_size = device_get_config_int("size");
dev->start_addr = device_get_config_int("start");
@@ -984,6 +986,96 @@ static const device_t ev159_device = {
};
#ifdef USE_ISAMEM_BRAT
static const device_config_t brat_config[] =
{
{
"base", "Address", CONFIG_HEX16, "", 0x0258, "", { 0 },
{
{
"208H", 0x0208
},
{
"218H", 0x0218
},
{
"258H", 0x0258
},
{
"268H", 0x0268
},
{
""
}
},
},
{
"frame", "Frame Address", CONFIG_HEX20, "", 0, "", { 0 },
{
{
"Disabled", 0x00000
},
{
"D000H", 0xD0000
},
{
"E000H", 0xE0000
},
{
""
}
},
},
{
"width", "I/O Width", CONFIG_SELECTION, "", 8, "", { 0 },
{
{
"8-bit", 8
},
{
"16-bit", 16
},
{
""
}
},
},
{
"speed", "Transfer Speed", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"Standard", 0
},
{
"High-Speed", 1
},
{
""
}
}
},
{
"size", "Memory Size", CONFIG_SPINNER, "", 128,
"",
{ 0, 8192, 512 },
{ 0 }
},
{
"", "", -1
}
};
static const device_t brat_device = {
"BocaRAM/AT",
DEVICE_ISA,
ISAMEM_BRAT_CARD,
isamem_init, isamem_close, NULL,
{ NULL }, NULL, NULL,
brat_config
};
#endif
#ifdef USE_ISAMEM_RAMPAGE
static const device_config_t rampage_config[] =
{

2
src/dma.c
View File

@@ -892,8 +892,10 @@ dma_page_write(uint16_t addr, uint8_t val, void *priv)
{
uint8_t convert[8] = CHANNELS;
#ifdef USE_DYNAREC
if ((addr == 0x84) && cpu_use_dynarec)
update_tsc();
#endif
addr &= 0x0f;
dmaregs[2][addr] = val;

8
src/include/86box/scsi_buslogic.h
View File

@@ -20,12 +20,14 @@
# define SCSI_BUSLOGIC_H
extern const device_t buslogic_542b_1991_device;
extern const device_t buslogic_device;
extern const device_t buslogic_542b_device;
extern const device_t buslogic_545s_device;
extern const device_t buslogic_542bh_device;
extern const device_t buslogic_545c_device;
extern const device_t buslogic_640a_device;
extern const device_t buslogic_445s_device;
extern const device_t buslogic_pci_device;
extern const device_t buslogic_445c_device;
extern const device_t buslogic_958d_pci_device;
extern void BuslogicDeviceReset(void *p);

1
src/include/86box/vid_svga.h
View File

@@ -274,6 +274,7 @@ extern void tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, voi
extern uint8_t tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *p, svga_t *svga);
extern void tvp3026_recalctimings(void *p, svga_t *svga);
extern void tvp3026_hwcursor_draw(svga_t *svga, int displine);
extern float tvp3026_getclock(int clock, void *p);
#ifdef EMU_DEVICE_H
extern const device_t ati68860_ramdac_device;

2
src/include/86box/video.h
View File

@@ -348,6 +348,7 @@ extern const device_t s3_diamond_stealth_vram_isa_device;
extern const device_t s3_ami_86c924_isa_device;
extern const device_t s3_metheus_86c928_isa_device;
extern const device_t s3_metheus_86c928_vlb_device;
extern const device_t s3_spea_mercury_lite_86c928_pci_device;
extern const device_t s3_spea_mirage_86c801_isa_device;
extern const device_t s3_spea_mirage_86c805_vlb_device;
extern const device_t s3_mirocrystal_8s_805_vlb_device;
@@ -394,6 +395,7 @@ extern const device_t s3_trio64v2_dx_onboard_pci_device;
extern const device_t s3_virge_325_pci_device;
extern const device_t s3_diamond_stealth_2000_pci_device;
extern const device_t s3_diamond_stealth_3000_pci_device;
extern const device_t s3_stb_velocity_3d_pci_device;
extern const device_t s3_virge_375_pci_device;
extern const device_t s3_diamond_stealth_2000pro_pci_device;
extern const device_t s3_virge_385_pci_device;

8
src/scsi/scsi.c
View File

@@ -64,9 +64,10 @@ static SCSI_CARD scsi_cards[] = {
{ "aha154xc", &aha154xc_device, },
{ "aha154xcf", &aha154xcf_device, },
{ "aha154xcp", &aha154xcp_device, },
{ "bt542b", &buslogic_542b_1991_device, },
{ "bt542bh", &buslogic_device, },
{ "bt542b", &buslogic_542b_device, },
{ "bt542bh", &buslogic_542bh_device, },
{ "bt545s", &buslogic_545s_device, },
{ "bt545c", &buslogic_545c_device, },
{ "lcs6821n", &scsi_lcs6821n_device, },
{ "rt1000b", &scsi_rt1000b_device, },
{ "t128", &scsi_t128_device, },
@@ -78,7 +79,7 @@ static SCSI_CARD scsi_cards[] = {
{ "bt640a", &buslogic_640a_device, },
{ "ncr53c90", &ncr53c90_mca_device, },
{ "spock", &spock_device, },
{ "bt958d", &buslogic_pci_device, },
{ "bt958d", &buslogic_958d_pci_device, },
{ "ncr53c810", &ncr53c810_pci_device, },
{ "ncr53c815", &ncr53c815_pci_device, },
{ "ncr53c820", &ncr53c820_pci_device, },
@@ -87,6 +88,7 @@ static SCSI_CARD scsi_cards[] = {
{ "ncr53c875", &ncr53c875_pci_device, },
{ "dc390", &dc390_pci_device, },
{ "bt445s", &buslogic_445s_device, },
{ "bt445c", &buslogic_445c_device, },
{ "", NULL, },
};

426
src/scsi/scsi_buslogic.c
View File

@@ -231,13 +231,14 @@ typedef struct {
enum {
CHIP_BUSLOGIC_ISA_542_1991,
CHIP_BUSLOGIC_ISA_542,
CHIP_BUSLOGIC_ISA,
CHIP_BUSLOGIC_MCA,
CHIP_BUSLOGIC_EISA,
CHIP_BUSLOGIC_VLB,
CHIP_BUSLOGIC_PCI
CHIP_BUSLOGIC_ISA_542B_1991_12_14,
CHIP_BUSLOGIC_ISA_545S_1992_10_05,
CHIP_BUSLOGIC_ISA_542BH_1993_05_23,
CHIP_BUSLOGIC_ISA_545C_1994_12_01,
CHIP_BUSLOGIC_VLB_445S_1993_11_16,
CHIP_BUSLOGIC_VLB_445C_1994_12_01,
CHIP_BUSLOGIC_MCA_640A_1993_05_23,
CHIP_BUSLOGIC_PCI_958D_1995_12_30
};
@@ -266,17 +267,21 @@ BuslogicGetNVRFileName(buslogic_data_t *bl)
{
switch(bl->chip)
{
case CHIP_BUSLOGIC_ISA_542_1991:
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
return "bt542b.nvr";
case CHIP_BUSLOGIC_ISA_542:
return "bt542bh.nvr";
case CHIP_BUSLOGIC_ISA:
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
return "bt545s.nvr";
case CHIP_BUSLOGIC_MCA:
return "bt640a.nvr";
case CHIP_BUSLOGIC_VLB:
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
return "bt542bh.nvr";
case CHIP_BUSLOGIC_ISA_545C_1994_12_01:
return "bt545c.nvr";
case CHIP_BUSLOGIC_VLB_445S_1993_11_16:
return "bt445s.nvr";
case CHIP_BUSLOGIC_PCI:
case CHIP_BUSLOGIC_VLB_445C_1994_12_01:
return "bt445c.nvr";
case CHIP_BUSLOGIC_MCA_640A_1993_05_23:
return "bt640a.nvr";
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
return "bt958d.nvr";
default:
fatal("Unrecognized BusLogic chip: %i\n", bl->chip);
@@ -303,30 +308,36 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
HALR->structured.autoSCSIData.aHostAdaptertype[0] = ' ';
HALR->structured.autoSCSIData.aHostAdaptertype[5] = ' ';
switch (bl->chip) {
case CHIP_BUSLOGIC_ISA_542_1991:
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "542B", 4);
break;
case CHIP_BUSLOGIC_ISA_542:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "542BH", 5);
break;
case CHIP_BUSLOGIC_ISA:
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "545S", 4);
break;
case CHIP_BUSLOGIC_MCA:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "640A", 4);
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "542BH", 5);
break;
case CHIP_BUSLOGIC_VLB:
case CHIP_BUSLOGIC_ISA_545C_1994_12_01:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "545C", 4);
break;
case CHIP_BUSLOGIC_VLB_445S_1993_11_16:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "445S", 4);
break;
case CHIP_BUSLOGIC_PCI:
case CHIP_BUSLOGIC_VLB_445C_1994_12_01:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "445C", 4);
break;
case CHIP_BUSLOGIC_MCA_640A_1993_05_23:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "640A", 4);
break;
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "958D", 4);
break;
}
HALR->structured.autoSCSIData.fLevelSensitiveInterrupt = (bl->chip == CHIP_BUSLOGIC_PCI) ? 1 : 0;
HALR->structured.autoSCSIData.fLevelSensitiveInterrupt = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
HALR->structured.autoSCSIData.uSystemRAMAreForBIOS = 6;
if (bl->chip != CHIP_BUSLOGIC_PCI) {
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
switch(dev->DmaChannel) {
case 5:
HALR->structured.autoSCSIData.uDMAChannel = 1;
@@ -342,9 +353,9 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
break;
}
}
HALR->structured.autoSCSIData.fDMAAutoConfiguration = (bl->chip == CHIP_BUSLOGIC_PCI) ? 0 : 1;
HALR->structured.autoSCSIData.fDMAAutoConfiguration = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 1;
if (bl->chip != CHIP_BUSLOGIC_PCI) {
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
switch(dev->Irq) {
case 9:
HALR->structured.autoSCSIData.uIrqChannel = 1;
@@ -369,14 +380,14 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
break;
}
}
HALR->structured.autoSCSIData.fIrqAutoConfiguration = (bl->chip == CHIP_BUSLOGIC_PCI) ? 0 : 1;
HALR->structured.autoSCSIData.fIrqAutoConfiguration = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 1;
HALR->structured.autoSCSIData.uDMATransferRate = (bl->chip == CHIP_BUSLOGIC_PCI) ? 0 : 1;
HALR->structured.autoSCSIData.uDMATransferRate = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 1;
HALR->structured.autoSCSIData.uSCSIId = 7;
HALR->structured.autoSCSIData.uSCSIConfiguration = 0x3F;
HALR->structured.autoSCSIData.uBusOnDelay = (bl->chip == CHIP_BUSLOGIC_PCI) ? 0 : 7;
HALR->structured.autoSCSIData.uBusOffDelay = (bl->chip == CHIP_BUSLOGIC_PCI) ? 0 : 4;
HALR->structured.autoSCSIData.uBusOnDelay = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 7;
HALR->structured.autoSCSIData.uBusOffDelay = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 4;
HALR->structured.autoSCSIData.uBIOSConfiguration = (bl->has_bios) ? 0x33 : 0x32;
if (!safe)
HALR->structured.autoSCSIData.uBIOSConfiguration |= 0x04;
@@ -416,7 +427,7 @@ BuslogicInitializeAutoSCSIRam(x54x_t *dev)
fatal("BuslogicInitializeAutoSCSIRam(): Error reading data\n");
fclose(f);
f = NULL;
if (bl->chip == CHIP_BUSLOGIC_PCI) {
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
x54x_io_remove(dev, dev->Base, 4);
switch(HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
case 0:
@@ -472,7 +483,10 @@ buslogic_get_host_id(void *p)
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
return dev->HostID;
else
return HALR->structured.autoSCSIData.uSCSIId;
@@ -489,7 +503,11 @@ buslogic_get_irq(void *p)
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991) || (bl->chip == CHIP_BUSLOGIC_PCI))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) ||
(bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
return dev->Irq;
else
return bl_irq[HALR->structured.autoSCSIData.uIrqChannel];
@@ -506,9 +524,12 @@ buslogic_get_dma(void *p)
HALocalRAM *HALR = &bl->LocalRAM;
if (bl->chip == CHIP_BUSLOGIC_PCI)
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30)
return (dev->Base ? 7 : 0);
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991))
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
return dev->DmaChannel;
else
return bl_dma[HALR->structured.autoSCSIData.uDMAChannel];
@@ -543,15 +564,15 @@ buslogic_param_len(void *p)
case 0xFB:
return 3;
case 0x93: /* Valid only for VLB */
return (bl->chip == CHIP_BUSLOGIC_VLB) ? 1 : 0;
return (bl->chip == CHIP_BUSLOGIC_VLB_445C_1994_12_01 || bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) ? 1 : 0;
case 0x95: /* Valid only for PCI */
return (bl->chip == CHIP_BUSLOGIC_PCI) ? 1 : 0;
return (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
case 0x97: /* Valid only for PCI */
case 0xA7: /* Valid only for PCI */
return (bl->chip == CHIP_BUSLOGIC_PCI) ? 10 : 0;
return (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 10 : 0;
case 0xA8: /* Valid only for PCI */
case 0xA9: /* Valid only for PCI */
return (bl->chip == CHIP_BUSLOGIC_PCI) ? 4 : 0;
return (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 4 : 0;
default:
return 0;
}
@@ -690,6 +711,8 @@ buslogic_cmds(void *p)
BuslogicPCIInformation_t *ReplyPI;
int cCharsToTransfer;
buslogic_log("Buslogic cmds = 0x%02x\n", dev->Command);
switch (dev->Command) {
case 0x20:
dev->DataReplyLeft = 0;
@@ -754,7 +777,7 @@ buslogic_cmds(void *p)
case 0x84:
dev->DataBuf[0] = dev->fw_rev[4];
dev->DataReplyLeft = 1;
break;
break;
case 0x85:
if (strlen(dev->fw_rev) == 6)
dev->DataBuf[0] = dev->fw_rev[5];
@@ -763,7 +786,7 @@ buslogic_cmds(void *p)
dev->DataReplyLeft = 1;
break;
case 0x86:
if (bl->chip == CHIP_BUSLOGIC_PCI) {
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
ReplyPI = (BuslogicPCIInformation_t *) dev->DataBuf;
memset(ReplyPI, 0, sizeof(BuslogicPCIInformation_t));
ReplyPI->InformationIsValid = 0;
@@ -801,7 +824,7 @@ buslogic_cmds(void *p)
/* The reply length is set by the guest and is found in the first byte of the command buffer. */
dev->DataReplyLeft = dev->CmdBuf[0];
memset(dev->DataBuf, 0, dev->DataReplyLeft);
if (bl->chip == CHIP_BUSLOGIC_ISA_542)
if (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23)
i = 5;
else
i = 4;
@@ -819,16 +842,18 @@ buslogic_cmds(void *p)
memset(ReplyIESI, 0, sizeof(ReplyInquireExtendedSetupInformation));
switch (bl->chip) {
case CHIP_BUSLOGIC_ISA_542_1991:
case CHIP_BUSLOGIC_ISA_542:
case CHIP_BUSLOGIC_ISA:
case CHIP_BUSLOGIC_VLB:
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
case CHIP_BUSLOGIC_ISA_545C_1994_12_01:
case CHIP_BUSLOGIC_VLB_445S_1993_11_16:
case CHIP_BUSLOGIC_VLB_445C_1994_12_01:
ReplyIESI->uBusType = 'A'; /* ISA style */
break;
case CHIP_BUSLOGIC_MCA:
case CHIP_BUSLOGIC_MCA_640A_1993_05_23:
ReplyIESI->uBusType = 'M'; /* MCA style */
break;
case CHIP_BUSLOGIC_PCI:
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
ReplyIESI->uBusType = 'E'; /* PCI style */
break;
}
@@ -836,17 +861,19 @@ buslogic_cmds(void *p)
ReplyIESI->u16ScatterGatherLimit = 8192;
ReplyIESI->cMailbox = dev->MailboxCount;
ReplyIESI->uMailboxAddressBase = dev->MailboxOutAddr;
ReplyIESI->fHostWideSCSI = 1; /* This should be set for the BT-542B as well. */
if ((bl->chip != CHIP_BUSLOGIC_ISA_542) && (bl->chip != CHIP_BUSLOGIC_ISA_542_1991) && (bl->chip != CHIP_BUSLOGIC_MCA))
ReplyIESI->fHostWideSCSI = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) &&
(bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23) &&
(bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16))
ReplyIESI->fLevelSensitiveInterrupt = bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt;
if (bl->chip == CHIP_BUSLOGIC_PCI)
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30)
ReplyIESI->fHostUltraSCSI = 1;
memcpy(ReplyIESI->aFirmwareRevision, &(dev->fw_rev[strlen(dev->fw_rev) - 3]), sizeof(ReplyIESI->aFirmwareRevision));
buslogic_log("Return Extended Setup Information: %d\n", dev->CmdBuf[0]);
break;
case 0x8F:
bl->fAggressiveRoundRobinMode = dev->CmdBuf[0] & 1;
buslogic_log("Aggressive Round Robin Mode = %d\n", bl->fAggressiveRoundRobinMode);
dev->DataReplyLeft = 0;
break;
case 0x90:
@@ -866,13 +893,16 @@ buslogic_cmds(void *p)
dev->DataReply = 0;
break;
case 0x93:
if (bl->chip != CHIP_BUSLOGIC_VLB) {
if ((bl->chip != CHIP_BUSLOGIC_VLB_445C_1994_12_01) && (bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
}
case 0x92:
if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991) || (bl->chip == CHIP_BUSLOGIC_MCA)) {
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -901,7 +931,7 @@ buslogic_cmds(void *p)
break;
}
if ((bl->chip == CHIP_BUSLOGIC_PCI) && !(dev->Status & STAT_INVCMD)) {
if ((bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) && !(dev->Status & STAT_INVCMD)) {
x54x_io_remove(dev, dev->Base, 4);
switch(HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
case 0:
@@ -918,7 +948,8 @@ buslogic_cmds(void *p)
}
break;
case 0x94:
if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991) || (bl->chip == CHIP_BUSLOGIC_MCA)) {
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -937,7 +968,7 @@ buslogic_cmds(void *p)
}
break;
case 0x95:
if (bl->chip == CHIP_BUSLOGIC_PCI) {
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
if (dev->Base != 0)
x54x_io_remove(dev, dev->Base, 4);
if (dev->CmdBuf[0] < 6) {
@@ -966,7 +997,7 @@ buslogic_cmds(void *p)
dev->DataReplyLeft = 0;
break;
case 0xA8:
if (bl->chip != CHIP_BUSLOGIC_PCI) {
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -985,7 +1016,7 @@ buslogic_cmds(void *p)
dev->DataReply = 0;
break;
case 0xA9:
if (bl->chip != CHIP_BUSLOGIC_PCI) {
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -1038,18 +1069,20 @@ buslogic_setup_data(void *p)
bl_setup->uCharacterD = 'D'; /* BusLogic model. */
switch(bl->chip)
{
case CHIP_BUSLOGIC_ISA_542_1991:
case CHIP_BUSLOGIC_ISA_542:
case CHIP_BUSLOGIC_ISA:
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
case CHIP_BUSLOGIC_ISA_545C_1994_12_01:
bl_setup->uHostBusType = 'A';
break;
case CHIP_BUSLOGIC_MCA:
case CHIP_BUSLOGIC_MCA_640A_1993_05_23:
bl_setup->uHostBusType = 'B';
break;
case CHIP_BUSLOGIC_VLB:
case CHIP_BUSLOGIC_VLB_445S_1993_11_16:
case CHIP_BUSLOGIC_VLB_445C_1994_12_01:
bl_setup->uHostBusType = 'E';
break;
case CHIP_BUSLOGIC_PCI:
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
bl_setup->uHostBusType = 'F';
break;
}
@@ -1062,6 +1095,8 @@ buslogic_is_aggressive_mode(void *p)
x54x_t *dev = (x54x_t *)p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
buslogic_log("Buslogic: Aggressive mode = %d\n", bl->fAggressiveRoundRobinMode);
return bl->fAggressiveRoundRobinMode;
}
@@ -1072,7 +1107,8 @@ buslogic_interrupt_type(void *p)
x54x_t *dev = (x54x_t *)p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542) || (bl->chip == CHIP_BUSLOGIC_ISA_542_1991) || (bl->chip == CHIP_BUSLOGIC_MCA))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23))
return 0;
else
return !!bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt;
@@ -1302,7 +1338,7 @@ static void
BuslogicInitializeLocalRAM(buslogic_data_t *bl)
{
memset(bl->LocalRAM.u8View, 0, sizeof(HALocalRAM));
if (bl->chip == CHIP_BUSLOGIC_PCI) {
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt = 1;
} else {
bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt = 0;
@@ -1582,92 +1618,115 @@ buslogic_init(const device_t *info)
bl->fAggressiveRoundRobinMode = 1;
switch(bl->chip)
{
case CHIP_BUSLOGIC_ISA_542_1991:
strcpy(dev->name, "BT-542B");
bios_rom_name = "roms/scsi/buslogic/BT-542B_BIOS.ROM";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA221";
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_ISA_542:
strcpy(dev->name, "BT-542BH");
bios_rom_name = "roms/scsi/buslogic/BT-542BH_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA335";
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_ISA:
default:
strcpy(dev->name, "BT-545S");
bios_rom_name = "roms/scsi/buslogic/BT-545S_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-545S_AutoSCSI.rom";
autoscsi_rom_size = 0x4000;
has_scam_rom = 0;
dev->fw_rev = "AA421E";
dev->ha_bps = 10000000.0; /* fast SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_MCA:
strcpy(dev->name, "BT-640A");
bios_rom_name = "roms/scsi/buslogic/BT-640A_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "BA150";
dev->flags |= X54X_32BIT;
dev->pos_regs[0] = 0x08; /* MCA board ID */
dev->pos_regs[1] = 0x07;
mca_add(buslogic_mca_read, buslogic_mca_write, buslogic_mca_feedb, NULL, dev);
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_VLB:
strcpy(dev->name, "BT-445S");
bios_rom_name = "roms/scsi/buslogic/BT-445S_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-445S_AutoSCSI.rom";
autoscsi_rom_size = 0x8000;
has_scam_rom = 1;
scam_rom_name = "roms/scsi/buslogic/BT-445S_SCAM.rom";
scam_rom_size = 0x0200;
dev->fw_rev = "AA507B";
dev->flags |= X54X_32BIT;
dev->ha_bps = 10000000.0; /* fast SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_PCI:
strcpy(dev->name, "BT-958D");
bios_rom_name = "roms/scsi/buslogic/BT-958D_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-958D_AutoSCSI.rom";
autoscsi_rom_size = 0x8000;
has_scam_rom = 1;
scam_rom_name = "roms/scsi/buslogic/BT-958D_SCAM.rom";
scam_rom_size = 0x0200;
dev->fw_rev = "AA507B";
dev->flags |= (X54X_CDROM_BOOT | X54X_32BIT);
dev->ha_bps = 20000000.0; /* ultra SCSI */
dev->max_id = 15; /* wide SCSI */
break;
}
bios_rom_name = NULL;
has_autoscsi_rom = 0;
has_scam_rom = 0;
switch (bl->chip) {
case CHIP_BUSLOGIC_ISA_542B_1991_12_14: /*Dated December 14th, 1991*/
strcpy(dev->name, "BT-542B");
bios_rom_name = "roms/scsi/buslogic/BT-542B_BIOS.ROM";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA221";
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_ISA_545S_1992_10_05: /*Dated October 5th, 1992*/
strcpy(dev->name, "BT-545S");
bios_rom_name = "roms/scsi/buslogic/BT-545S_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA331";
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23: /*Dated May 23rd, 1993*/
strcpy(dev->name, "BT-542BH");
bios_rom_name = "roms/scsi/buslogic/BT-542BH_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA335";
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_ISA_545C_1994_12_01: /*Dated December 1st, 1994*/
strcpy(dev->name, "BT-545C");
bios_rom_name = "roms/scsi/buslogic/BT-545C_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-545C_AutoSCSI.rom";
autoscsi_rom_size = 0x4000;
has_scam_rom = 0;
dev->fw_rev = "AA425J";
dev->ha_bps = 10000000.0; /* fast SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_MCA_640A_1993_05_23: /*Dated May 23rd, 1993*/
strcpy(dev->name, "BT-640A");
bios_rom_name = "roms/scsi/buslogic/BT-640A_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "BA335";
dev->flags |= X54X_32BIT;
dev->pos_regs[0] = 0x08; /* MCA board ID */
dev->pos_regs[1] = 0x07;
mca_add(buslogic_mca_read, buslogic_mca_write, buslogic_mca_feedb, NULL, dev);
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_VLB_445S_1993_11_16: /*Dated November 16th, 1993*/
strcpy(dev->name, "BT-445S");
bios_rom_name = "roms/scsi/buslogic/BT-445S_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 0;
has_scam_rom = 0;
dev->fw_rev = "AA335";
dev->flags |= X54X_32BIT;
dev->ha_bps = 5000000.0; /* normal SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_VLB_445C_1994_12_01: /*Dated December 1st, 1994*/
strcpy(dev->name, "BT-445C");
bios_rom_name = "roms/scsi/buslogic/BT-445C_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-445C_AutoSCSI.rom";
autoscsi_rom_size = 0x4000;
has_scam_rom = 0;
dev->fw_rev = "AA425J";
dev->flags |= X54X_32BIT;
dev->ha_bps = 10000000.0; /* fast SCSI */
dev->max_id = 7; /* narrow SCSI */
break;
case CHIP_BUSLOGIC_PCI_958D_1995_12_30: /*Dated December 30th, 1995*/
strcpy(dev->name, "BT-958D");
bios_rom_name = "roms/scsi/buslogic/BT-958D_BIOS.rom";
bios_rom_size = 0x4000;
bios_rom_mask = 0x3fff;
has_autoscsi_rom = 1;
autoscsi_rom_name = "roms/scsi/buslogic/BT-958D_AutoSCSI.rom";
autoscsi_rom_size = 0x8000;
has_scam_rom = 1;
scam_rom_name = "roms/scsi/buslogic/BT-958D_SCAM.rom";
scam_rom_size = 0x0200;
dev->fw_rev = "AA507B";
dev->flags |= (X54X_CDROM_BOOT | X54X_32BIT);
dev->ha_bps = 20000000.0; /* ultra SCSI */
dev->max_id = 15; /* wide SCSI */
break;
}
if ((dev->Base != 0) && !(dev->card_bus & DEVICE_MCA) && !(dev->card_bus & DEVICE_PCI)) {
x54x_io_set(dev, dev->Base, 4);
@@ -1709,7 +1768,7 @@ buslogic_init(const device_t *info)
bl->bios_mask = 0;
}
if (bl->chip == CHIP_BUSLOGIC_PCI) {
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
dev->pci_slot = pci_add_card(PCI_ADD_NORMAL, BuslogicPCIRead, BuslogicPCIWrite, dev);
buslogic_pci_bar[0].addr_regs[0] = 1;
@@ -1727,14 +1786,15 @@ buslogic_init(const device_t *info)
x54x_mem_disable(dev);
}
if ((bl->chip == CHIP_BUSLOGIC_MCA) || (bl->chip == CHIP_BUSLOGIC_PCI))
if ((bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
mem_mapping_disable(&bl->bios.mapping);
buslogic_log("Buslogic on port 0x%04X\n", dev->Base);
x54x_device_reset(dev);
if ((bl->chip != CHIP_BUSLOGIC_ISA_542) && (bl->chip != CHIP_BUSLOGIC_ISA_542_1991) && (bl->chip != CHIP_BUSLOGIC_MCA)) {
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) && (bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) &&
(bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
BuslogicInitializeLocalRAM(bl);
BuslogicInitializeAutoSCSIRam(dev);
}
@@ -1848,19 +1908,10 @@ static const device_config_t BT958D_Config[] = {
}
};
const device_t buslogic_542b_1991_device = {
const device_t buslogic_542b_device = {
"BusLogic BT-542B ISA",
DEVICE_ISA | DEVICE_AT,
CHIP_BUSLOGIC_ISA_542_1991,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
};
const device_t buslogic_device = {
"BusLogic BT-542BH ISA",
DEVICE_ISA | DEVICE_AT,
CHIP_BUSLOGIC_ISA_542,
CHIP_BUSLOGIC_ISA_542B_1991_12_14,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
@@ -1869,7 +1920,25 @@ const device_t buslogic_device = {
const device_t buslogic_545s_device = {
"BusLogic BT-545S ISA",
DEVICE_ISA | DEVICE_AT,
CHIP_BUSLOGIC_ISA,
CHIP_BUSLOGIC_ISA_545S_1992_10_05,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
};
const device_t buslogic_542bh_device = {
"BusLogic BT-542BH ISA",
DEVICE_ISA | DEVICE_AT,
CHIP_BUSLOGIC_ISA_542BH_1993_05_23,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
};
const device_t buslogic_545c_device = {
"BusLogic BT-545C ISA",
DEVICE_ISA | DEVICE_AT,
CHIP_BUSLOGIC_ISA_545C_1994_12_01,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
@@ -1878,7 +1947,7 @@ const device_t buslogic_545s_device = {
const device_t buslogic_640a_device = {
"BusLogic BT-640A MCA",
DEVICE_MCA,
CHIP_BUSLOGIC_MCA,
CHIP_BUSLOGIC_MCA_640A_1993_05_23,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
NULL
@@ -1887,16 +1956,25 @@ const device_t buslogic_640a_device = {
const device_t buslogic_445s_device = {
"BusLogic BT-445S VLB",
DEVICE_VLB,
CHIP_BUSLOGIC_VLB,
CHIP_BUSLOGIC_VLB_445S_1993_11_16,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
};
const device_t buslogic_pci_device = {
const device_t buslogic_445c_device = {
"BusLogic BT-445C VLB",
DEVICE_VLB,
CHIP_BUSLOGIC_VLB_445C_1994_12_01,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT_ISA_Config
};
const device_t buslogic_958d_pci_device = {
"BusLogic BT-958D PCI",
DEVICE_PCI,
CHIP_BUSLOGIC_PCI,
CHIP_BUSLOGIC_PCI_958D_1995_12_30,
buslogic_init, x54x_close, NULL,
{ NULL }, NULL, NULL,
BT958D_Config

149
src/video/vid_s3.c
View File

@@ -41,6 +41,7 @@
#define ROM_DIAMOND_STEALTH_VRAM "roms/video/s3/Diamond Stealth VRAM BIOS v2.31 U14.BIN"
#define ROM_AMI_86C924 "roms/video/s3/S3924AMI.BIN"
#define ROM_METHEUS_86C928 "roms/video/s3/928.VBI"
#define ROM_SPEA_MERCURY_LITE_PCI "roms/video/s3/SPEAVGA.VBI"
#define ROM_SPEA_MIRAGE_86C801 "roms/video/s3/V7MIRAGE.VBI"
#define ROM_SPEA_MIRAGE_86C805 "roms/video/s3/86c805pspeavlbus.BIN"
#define ROM_MIROCRYSTAL8S_805 "roms/video/s3/S3_805VL_ATT20C491_miroCRYSTAL_8s_ver1.4.BIN"
@@ -104,7 +105,8 @@ enum
S3_PHOENIX_VISION968,
S3_MIROCRYSTAL8S_805,
S3_NUMBER9_9FX_531,
S3_NUMBER9_9FX_771
S3_NUMBER9_9FX_771,
S3_SPEA_MERCURY_LITE_PCI
};
@@ -113,22 +115,24 @@ enum
S3_86C911 = 0x00,
S3_86C924 = 0x02,
S3_86C928 = 0x04,
S3_86C801 = 0x06,
S3_86C805 = 0x07,
S3_VISION964 = 0x08,
S3_VISION968 = 0x10,
S3_VISION864 = 0x18,
S3_VISION868 = 0x20,
S3_TRIO32 = 0x28,
S3_TRIO64 = 0x30,
S3_TRIO64V = 0x38,
S3_TRIO64V2 = 0x40
S3_86C928PCI = 0x06,
S3_86C801 = 0x07,
S3_86C805 = 0x08,
S3_VISION964 = 0x18,
S3_VISION968 = 0x20,
S3_VISION864 = 0x28,
S3_VISION868 = 0x30,
S3_TRIO32 = 0x38,
S3_TRIO64 = 0x40,
S3_TRIO64V = 0x48,
S3_TRIO64V2 = 0x50
};
static video_timings_t timing_s3_86c911 = {VIDEO_ISA, 4, 4, 5, 20, 20, 35};
static video_timings_t timing_s3_86c801 = {VIDEO_ISA, 4, 4, 5, 20, 20, 35};
static video_timings_t timing_s3_86c805 = {VIDEO_BUS, 4, 4, 5, 20, 20, 35};
static video_timings_t timing_s3_86c928pci = {VIDEO_PCI, 2, 2, 4, 26, 26, 42};
static video_timings_t timing_s3_stealth64_vlb = {VIDEO_BUS, 2, 2, 4, 26, 26, 42};
static video_timings_t timing_s3_stealth64_pci = {VIDEO_PCI, 2, 2, 4, 26, 26, 42};
static video_timings_t timing_s3_vision864_vlb = {VIDEO_BUS, 4, 4, 5, 20, 20, 35};
@@ -563,7 +567,7 @@ static void
s3_accel_out_pixtrans_w(s3_t *s3, uint16_t val)
{
svga_t *svga = &s3->svga;
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
@@ -1173,7 +1177,8 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
else
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[0] << 8), s3);
} else {
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[0] << 8), s3);
if (s3->chip != S3_86C928PCI)
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[0] << 8), s3);
}
break;
}
@@ -1197,7 +1202,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
}
break;
case 0x200:
/*Windows 95's built-in driver expects this to be loaded regardless of the byte swap bit (0xE2E9) in the 86c928*/
/*Windows 95's built-in driver expects this to be loaded regardless of the byte swap bit (0xE2E9) in the 86c928 ISA/VLB*/
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
@@ -1205,7 +1210,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
else
s3_accel_start(16, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), 0, s3);
} else {
if (s3->chip == S3_86C928)
if (s3->chip == S3_86C928 || s3->chip == S3_86C928PCI)
s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8));
else {
if (s3->accel.cmd & 0x1000)
@@ -1214,6 +1219,15 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
}
}
} else {
if (s3->chip == S3_86C928 || s3->chip == S3_86C928PCI)
s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8));
else {
if (s3->accel.cmd & 0x1000)
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3);
else
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
}
}
break;
case 0x400:
@@ -1261,7 +1275,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
s3_accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
break;
case 0x200:
/*Windows 95's built-in driver expects the upper 16 bits to be loaded instead of the whole 32-bit one, regardless of the byte swap bit (0xE2EB) in the 86c928*/
/*Windows 95's built-in driver expects the upper 16 bits to be loaded instead of the whole 32-bit one, regardless of the byte swap bit (0xE2EB) in the 86c928 ISA/VLB card*/
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
@@ -1269,7 +1283,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
else
s3_accel_start(16, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
} else {
if (s3->chip == S3_86C928)
if (s3->chip == S3_86C928 || s3->chip == S3_86C928PCI)
s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[2] | (s3->accel.pix_trans[3] << 8));
else {
if (s3->accel.cmd & 0x1000)
@@ -1278,6 +1292,15 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
}
} else {
if (s3->chip == S3_86C928 || s3->chip == S3_86C928PCI)
s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[2] | (s3->accel.pix_trans[3] << 8));
else {
if (s3->accel.cmd & 0x1000)
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
else
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
}
break;
case 0x400:
@@ -1360,7 +1383,7 @@ s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val)
if ((addr >= 0x08000) && (addr <= 0x0803f))
s3_pci_write(0, addr & 0xff, val, s3);
}
switch (addr & 0x1fffe) {
case 0x8100: addr = 0x82e8; break; /*ALT_CURXY*/
case 0x8102: addr = 0x86e8; break;
@@ -2405,8 +2428,10 @@ s3_out(uint16_t addr, uint8_t val, void *p)
{
case 0x3c2:
if ((s3->chip == S3_VISION964) || (s3->chip == S3_VISION968) || (s3->chip == S3_86C928)) {
if (((val >> 2) & 3) != 3)
icd2061_write(svga->clock_gen, (val >> 2) & 3);
if ((s3->card_type != S3_SPEA_MERCURY_P64V) && (s3->card_type != S3_MIROVIDEO40SV_ERGO_968)) {
if (((val >> 2) & 3) != 3)
icd2061_write(svga->clock_gen, (val >> 2) & 3);
}
}
break;
@@ -2472,6 +2497,8 @@ s3_out(uint16_t addr, uint8_t val, void *p)
sc1148x_ramdac_out(addr, rs2, val, svga->ramdac, svga);
} else if (s3->card_type == S3_NUMBER9_9FX_531)
att498_ramdac_out(addr, rs2, val, svga->ramdac, svga);
else if ((s3->chip == S3_86C928PCI) && (s3->card_type == S3_SPEA_MERCURY_LITE_PCI))
sc1502x_ramdac_out(addr, val, svga->ramdac, svga);
else
sdac_ramdac_out(addr, rs2, val, svga->ramdac, svga);
return;
@@ -2760,6 +2787,8 @@ s3_in(uint16_t addr, void *p)
return sc1148x_ramdac_in(addr, rs2, svga->ramdac, svga);
else if (s3->card_type == S3_NUMBER9_9FX_531)
return att498_ramdac_in(addr, rs2, svga->ramdac, svga);
else if ((s3->chip == S3_86C928PCI) && (s3->card_type == S3_SPEA_MERCURY_LITE_PCI))
return sc1502x_ramdac_in(addr, svga->ramdac, svga);
else
return sdac_ramdac_in(addr, rs2, svga->ramdac, svga);
break;
@@ -2880,7 +2909,7 @@ static void s3_recalctimings(svga_t *svga)
if (s3->card_type == S3_MIROCRYSTAL10SD_805 || s3->card_type == S3_MIROCRYSTAL20SD_864 ||
s3->card_type == S3_MIROCRYSTAL20SV_964 || s3->card_type == S3_SPEA_MIRAGE_86C801 ||
s3->card_type == S3_SPEA_MIRAGE_86C805 || s3->card_type == S3_MIROCRYSTAL8S_805 ||
s3->card_type == S3_NUMBER9_9FX_531) {
s3->card_type == S3_NUMBER9_9FX_531 || s3->card_type == S3_SPEA_MERCURY_LITE_PCI) {
if (!(svga->crtc[0x5e] & 0x04))
svga->vblankstart = svga->dispend;
if (svga->bpp != 32) {
@@ -3006,7 +3035,8 @@ static void s3_recalctimings(svga_t *svga)
svga->hdisp = s3->width;
}
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805)
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805 ||
s3->card_type == S3_SPEA_MERCURY_LITE_PCI)
svga->hdisp = s3->width;
break;
case 16:
@@ -3034,7 +3064,8 @@ static void s3_recalctimings(svga_t *svga)
svga->hdisp = s3->width;
}
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805)
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805 ||
s3->card_type == S3_SPEA_MERCURY_LITE_PCI)
svga->hdisp = s3->width;
break;
case 24:
@@ -3044,6 +3075,15 @@ static void s3_recalctimings(svga_t *svga)
svga->hdisp /= 3;
else
svga->hdisp = (svga->hdisp * 2) / 3;
if (s3->card_type == S3_SPEA_MERCURY_LITE_PCI) {
if (s3->width == 2048)
switch (svga->dispend) {
case 480:
svga->hdisp = 640;
break;
}
}
} else {
if (s3->card_type == S3_MIROVIDEO40SV_ERGO_968 || s3->card_type == S3_PHOENIX_VISION968 ||
s3->card_type == S3_SPEA_MERCURY_P64V)
@@ -3085,7 +3125,7 @@ static void s3_recalctimings(svga_t *svga)
s3->width = 800;
svga->hdisp = 800;
break;
}
}
}
}
}
@@ -3292,6 +3332,7 @@ s3_updatemapping(s3_t *s3)
case S3_TRIO64V:
case S3_TRIO64V2:
case S3_86C928:
case S3_86C928PCI:
s3->linear_size = 0x400000;
break;
default:
@@ -3842,8 +3883,9 @@ s3_accel_in(uint16_t port, void *p)
s3_accel_start(16, 1, s3->accel.pix_trans[0], 0, s3);
else
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
} else
} else {
s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
}
break;
}
}
@@ -5235,7 +5277,6 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_
/*Bit 4 of the Command register is the draw yes bit, which enables writing to memory/reading from memory when enabled.
When this bit is disabled, no writing to memory/reading from memory is allowed. (This bit is almost meaningless on
the NOP command)*/
switch (cmd)
{
case 0: /*NOP (Short Stroke Vectors)*/
@@ -6129,8 +6170,6 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
while ((s3->accel.poly_cy < end_y1) && (s3->accel.poly_cy2 < end_y2))
{
int y = s3->accel.poly_cy;
@@ -6278,7 +6317,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_
ROPMIX
if (s3->accel.cmd & 0x10) {
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.dx, out);
}
}
@@ -6615,6 +6654,7 @@ static void s3_reset(void *priv)
break;
case S3_METHEUS_86C928:
case S3_SPEA_MERCURY_LITE_PCI:
svga->crtc[0x5a] = 0x0a;
break;
@@ -6763,6 +6803,11 @@ static void *s3_init(const device_t *info)
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c801);
break;
case S3_SPEA_MERCURY_LITE_PCI:
bios_fn = ROM_SPEA_MERCURY_LITE_PCI;
chip = S3_86C928PCI;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c928pci);
break;
case S3_MIROCRYSTAL20SD_864:
bios_fn = ROM_MIROCRYSTAL20SD_864_VLB;
chip = S3_VISION864;
@@ -7159,7 +7204,20 @@ static void *s3_init(const device_t *info)
svga->ramdac = device_add(&bt485_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
break;
break;
case S3_SPEA_MERCURY_LITE_PCI:
svga->decode_mask = (4 << 20) - 1;
stepping = 0xb0; /*86C928PCI*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = stepping;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&sc1502x_ramdac_device);
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
break;
case S3_PARADISE_BAHAMAS64:
case S3_PHOENIX_VISION864:
@@ -7219,13 +7277,15 @@ static void *s3_init(const device_t *info)
}
if (info->local == S3_ELSAWIN2KPROX || info->local == S3_PHOENIX_VISION968 ||
info->local == S3_NUMBER9_9FX_771)
info->local == S3_NUMBER9_9FX_771) {
svga->ramdac = device_add(&ibm_rgb528_ramdac_device);
else
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
} else {
svga->ramdac = device_add(&tvp3026_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
svga->clock_gen = svga->ramdac;
svga->getclock = tvp3026_getclock;
}
break;
case S3_NUMBER9_9FX_531:
@@ -7380,6 +7440,11 @@ static int s3_metheus_86c928_available(void)
return rom_present(ROM_METHEUS_86C928);
}
static int s3_spea_mercury_lite_pci_available(void)
{
return rom_present(ROM_SPEA_MERCURY_LITE_PCI);
}
static int s3_bahamas64_available(void)
{
return rom_present(ROM_PARADISE_BAHAMAS64);
@@ -7796,6 +7861,20 @@ const device_t s3_metheus_86c928_vlb_device =
s3_standard_config
};
const device_t s3_spea_mercury_lite_86c928_pci_device =
{
"S3 86c928 PCI (SPEA Mercury Lite)",
DEVICE_PCI,
S3_SPEA_MERCURY_LITE_PCI,
s3_init,
s3_close,
s3_reset,
{ s3_spea_mercury_lite_pci_available },
s3_speed_changed,
s3_force_redraw,
s3_standard_config
};
const device_t s3_mirocrystal_20sd_864_vlb_device =
{
"S3 Vision864 VLB (MiroCRYSTAL 20SD)",

218
src/video/vid_s3_virge.c
View File

@@ -61,7 +61,7 @@ static int dither[4][4] =
#define FIFO_ENTRY_SIZE (1 << 31)
#define FIFO_ENTRIES (virge->fifo_write_idx - virge->fifo_read_idx)
#define FIFO_FULL ((virge->fifo_write_idx - virge->fifo_read_idx) >= FIFO_SIZE)
#define FIFO_FULL ((virge->fifo_write_idx - virge->fifo_read_idx) >= (FIFO_SIZE - 4))
#define FIFO_EMPTY (virge->fifo_read_idx == virge->fifo_write_idx)
#define FIFO_TYPE 0xff000000
@@ -70,6 +70,7 @@ static int dither[4][4] =
#define ROM_VIRGE_325 "roms/video/s3virge/86c325.bin"
#define ROM_DIAMOND_STEALTH3D_2000 "roms/video/s3virge/s3virge.bin"
#define ROM_DIAMOND_STEALTH3D_3000 "roms/video/s3virge/diamondstealth3000.vbi"
#define ROM_STB_VELOCITY_3D "roms/video/s3virge/stb_velocity3d_110.BIN"
#define ROM_VIRGE_DX "roms/video/s3virge/86c375_1.bin"
#define ROM_DIAMOND_STEALTH3D_2000PRO "roms/video/s3virge/virgedxdiamond.vbi"
#define ROM_VIRGE_GX "roms/video/s3virge/86c375_4.bin"
@@ -82,6 +83,7 @@ enum
S3_VIRGE_325,
S3_DIAMOND_STEALTH3D_2000,
S3_DIAMOND_STEALTH3D_3000,
S3_STB_VELOCITY_3D,
S3_VIRGE_DX,
S3_DIAMOND_STEALTH3D_2000PRO,
S3_VIRGE_GX,
@@ -288,7 +290,6 @@ typedef struct virge_t
int sec_x, sec_y, sec_w, sec_h;
} streams;
int fifo_slot;
uint8_t cmd_dma;
uint8_t dma_bs;
uint32_t cmd_dma_base;
@@ -302,6 +303,10 @@ typedef struct virge_t
fifo_entry_t fifo[FIFO_SIZE];
volatile int fifo_read_idx, fifo_write_idx;
thread_t *fifo_thread;
event_t *wake_fifo_thread;
event_t *fifo_not_full_event;
int virge_busy, local;
uint8_t subsys_stat, subsys_cntl, advfunc_cntl;
@@ -417,6 +422,11 @@ s3_virge_tri_timer(void *p)
thread_set_event(virge->wake_render_thread); /*Wake up FIFO thread if moving from idle*/
}
static __inline void
wake_fifo_thread(virge_t *virge)
{
thread_set_event(virge->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
static void
queue_triangle(virge_t *virge)
@@ -970,7 +980,8 @@ static void s3_virge_updatemapping(virge_t *virge)
mem_mapping_disable(&virge->new_mmio_mapping);
}
static void s3_virge_vblank_start(svga_t *svga)
static void
s3_virge_vblank_start(svga_t *svga)
{
virge_t *virge = (virge_t *)svga->p;
@@ -978,6 +989,16 @@ static void s3_virge_vblank_start(svga_t *svga)
s3_virge_update_irqs(virge);
}
static void
s3_virge_wait_fifo_idle(virge_t *virge)
{
while (!FIFO_EMPTY)
{
wake_fifo_thread(virge);
thread_wait_event(virge->fifo_not_full_event, 1);
}
}
static uint8_t
s3_virge_mmio_read(uint32_t addr, void *p)
{
@@ -989,14 +1010,12 @@ s3_virge_mmio_read(uint32_t addr, void *p)
switch (addr & 0xffff)
{
case 0x8505:
ret = 0;
if (virge->s3d_busy || virge->fifo_slot) {
ret = 0x10;
} else {
ret = 0x30;
}
if (virge->fifo_slot)
virge->fifo_slot--;
if (virge->s3d_busy || virge->virge_busy || !FIFO_EMPTY)
ret = 0x10;
else
ret = 0x10 | (1 << 5);
if (!virge->virge_busy)
wake_fifo_thread(virge);
return ret;
case 0x83b0: case 0x83b1: case 0x83b2: case 0x83b3:
@@ -1014,6 +1033,7 @@ s3_virge_mmio_read(uint32_t addr, void *p)
return s3_virge_in(addr & 0x3ff, virge);
case 0x859c:
s3_virge_wait_fifo_idle(virge);
return virge->cmd_dma;
case 0xff20: case 0xff21:
@@ -1030,22 +1050,21 @@ static uint16_t
s3_virge_mmio_read_w(uint32_t addr, void *p)
{
virge_t *virge = (virge_t *)p;
uint32_t ret = 0xffff;
uint16_t ret = 0xffff;
s3_virge_log("[%04X:%08X]: MMIO ReadW addr = %04x\n", CS, cpu_state.pc, addr & 0xfffe);
switch (addr & 0xfffe) {
case 0x8504:
if (!virge->fifo_slot)
if (FIFO_EMPTY)
virge->subsys_stat |= INT_FIFO_EMP;
ret |= virge->subsys_stat;
if (virge->fifo_slot)
virge->fifo_slot--;
ret |= 0x30; /*A bit of a workaround at the moment.*/
s3_virge_update_irqs(virge);
return ret;
return ret;
case 0x859c:
s3_virge_wait_fifo_idle(virge);
return virge->cmd_dma;
default:
@@ -1134,78 +1153,91 @@ s3_virge_mmio_read_l(uint32_t addr, void *p)
break;
case 0x8504:
if (virge->s3d_busy || virge->fifo_slot) {
if (virge->s3d_busy || virge->virge_busy || !FIFO_EMPTY)
ret = (0x10 << 8);
} else {
else
ret = (0x10 << 8) | (1 << 13);
if (!virge->s3d_busy)
virge->subsys_stat |= INT_3DF_EMP;
if (!virge->fifo_slot)
virge->subsys_stat |= INT_FIFO_EMP;
}
ret |= virge->subsys_stat;
if (virge->fifo_slot)
virge->fifo_slot--;
s3_virge_update_irqs(virge);
if (!virge->virge_busy)
wake_fifo_thread(virge);
dmahdr->dblword_read = 0;
dmahdr->dblword_write = 0;
break;
case 0x8590:
s3_virge_wait_fifo_idle(virge);
ret = virge->cmd_dma_base;
break;
case 0x8594:
s3_virge_wait_fifo_idle(virge);
break;
case 0x8598:
s3_virge_wait_fifo_idle(virge);
ret = virge->dma_ptr;
break;
case 0x859c:
s3_virge_wait_fifo_idle(virge);
ret = virge->cmd_dma;
break;
case 0xa4d4:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_base;
break;
case 0xa4d8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.dest_base;
break;
case 0xa4dc:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.clip_l << 16) | virge->s3d.clip_r;
break;
case 0xa4e0:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.clip_t << 16) | virge->s3d.clip_b;
break;
case 0xa4e4:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.dest_str << 16) | virge->s3d.src_str;
break;
case 0xa4e8: case 0xace8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.mono_pat_0;
break;
case 0xa4ec: case 0xacec:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.mono_pat_1;
break;
case 0xa4f0:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pat_bg_clr;
break;
case 0xa4f4:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pat_fg_clr;
break;
case 0xa4f8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_bg_clr;
break;
case 0xa4fc:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_fg_clr;
break;
case 0xa500:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.cmd_set;
break;
case 0xa504:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.r_width << 16) | virge->s3d.r_height;
break;
case 0xa508:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.rsrc_x << 16) | virge->s3d.rsrc_y;
break;
case 0xa50c:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.rdest_x << 16) | virge->s3d.rdest_y;
break;
@@ -1242,14 +1274,96 @@ s3_virge_mmio_read_l(uint32_t addr, void *p)
return ret;
}
static void
fifo_thread(void *param)
{
virge_t *virge = (virge_t *)param;
static void s3_virge_mmio_write(uint32_t addr, uint8_t val, void *p)
while (virge->fifo_thread_run)
{
thread_set_event(virge->fifo_not_full_event);
thread_wait_event(virge->wake_fifo_thread, -1);
thread_reset_event(virge->wake_fifo_thread);
virge->virge_busy = 1;
while (!FIFO_EMPTY)
{
uint64_t start_time = plat_timer_read();
uint64_t end_time;
uint32_t addr, val;
fifo_entry_t *fifo = &virge->fifo[virge->fifo_read_idx & FIFO_MASK];
addr = fifo->addr_type & FIFO_ADDR;
val = fifo->val;
switch (fifo->addr_type & FIFO_TYPE)
{
case FIFO_WRITE_BYTE:
if ((addr & 0xfffc) < 0x8000)
s3_virge_bitblt(virge, 8, val);
break;
case FIFO_WRITE_WORD:
if ((addr & 0xfffc) < 0x8000)
{
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 16, ((val >> 8) | (val << 8)) << 16);
else
s3_virge_bitblt(virge, 16, val);
}
break;
case FIFO_WRITE_DWORD:
if ((addr & 0xfffc) < 0x8000)
{
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24));
else
s3_virge_bitblt(virge, 32, val);
}
break;
}
virge->fifo_read_idx++;
fifo->addr_type = FIFO_INVALID;
if (FIFO_ENTRIES > 0xe000)
thread_set_event(virge->fifo_not_full_event);
end_time = plat_timer_read();
virge_time += end_time - start_time;
}
virge->virge_busy = 0;
virge->subsys_stat |= INT_FIFO_EMP | INT_3DF_EMP;
s3_virge_update_irqs(virge);
}
}
static void
s3_virge_queue(virge_t *virge, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &virge->fifo[virge->fifo_write_idx & FIFO_MASK];
if (FIFO_FULL)
{
thread_reset_event(virge->fifo_not_full_event);
if (FIFO_FULL)
thread_wait_event(virge->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
fifo->val = val;
fifo->addr_type = (addr & FIFO_ADDR) | type;
virge->fifo_write_idx++;
if (FIFO_ENTRIES > 0xe000 || FIFO_ENTRIES < 8)
wake_fifo_thread(virge);
}
static void
s3_virge_mmio_write(uint32_t addr, uint8_t val, void *p)
{
virge_t *virge = (virge_t *)p;
s3_virge_log("MMIO WriteB addr = %04x, val = %02x\n", addr & 0xffff, val);
if ((addr & 0xffff) < 0x8000) {
s3_virge_bitblt(virge, 8, val);
s3_virge_queue(virge, addr, val, FIFO_WRITE_BYTE);
} else {
switch (addr & 0xffff) {
case 0x83b0: case 0x83b1: case 0x83b2: case 0x83b3:
@@ -1286,10 +1400,7 @@ s3_virge_mmio_write_w(uint32_t addr, uint16_t val, void *p)
s3_virge_log("[%04X:%08X]: MMIO WriteW addr = %04x, val = %04x\n", CS, cpu_state.pc, addr & 0xfffe, val);
if ((addr & 0xfffe) < 0x8000) {
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 16, ((val >> 8) | (val << 8)) << 16);
else
s3_virge_bitblt(virge, 16, val);
s3_virge_queue(virge, addr, val, FIFO_WRITE_WORD);
} else {
if ((addr & 0xfffe) == 0x83d4) {
s3_virge_mmio_write(addr, val, virge);
@@ -1310,17 +1421,19 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
s3_virge_log("MMIO WriteL addr = %04x, val = %08x\n", addr & 0xfffc, val);
if ((addr & 0xfffc) < 0x8000) {
if ((addr & 0xe000) == 0) {
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24));
else
s3_virge_bitblt(virge, 32, val);
s3_virge_bitblt(virge, 32, val);
} else {
s3_virge_queue(virge, addr, val, FIFO_WRITE_DWORD);
}
if (virge->cmd_dma) {
dmahdr->datatype = 1;
}
} else {
if ((addr & 0xfffc) >= 0xa000)
virge->fifo_slot++;
if (virge->cmd_dma) {
dmahdr->datatype = 0;
}
@@ -3875,6 +3988,7 @@ static void s3_virge_reset(void *priv)
virge->svga.crtc[0x59] = 0x70;
break;
case S3_DIAMOND_STEALTH3D_3000:
case S3_STB_VELOCITY_3D:
virge->svga.crtc[0x59] = 0x70;
break;
case S3_VIRGE_GX2:
@@ -3950,6 +4064,9 @@ static void *s3_virge_init(const device_t *info)
case S3_DIAMOND_STEALTH3D_3000:
bios_fn = ROM_DIAMOND_STEALTH3D_3000;
break;
case S3_STB_VELOCITY_3D:
bios_fn = ROM_STB_VELOCITY_3D;
break;
case S3_VIRGE_DX:
bios_fn = ROM_VIRGE_DX;
break;
@@ -4041,6 +4158,7 @@ static void *s3_virge_init(const device_t *info)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_diamond_stealth3d_2000_pci);
break;
case S3_DIAMOND_STEALTH3D_3000:
case S3_STB_VELOCITY_3D:
virge->svga.decode_mask = (8 << 20) - 1;
virge->virge_id_high = 0x88;
virge->virge_id_low = 0x3d;
@@ -4135,6 +4253,11 @@ static void *s3_virge_init(const device_t *info)
virge->render_thread_run = 1;
virge->render_thread = thread_create(render_thread, virge);
virge->wake_fifo_thread = thread_create_event();
virge->fifo_not_full_event = thread_create_event();
virge->fifo_thread_run = 1;
virge->fifo_thread = thread_create(fifo_thread, virge);
timer_add(&virge->tri_timer, s3_virge_tri_timer, virge, 0);
virge->local = info->local;
@@ -4153,6 +4276,12 @@ static void s3_virge_close(void *p)
thread_destroy_event(virge->wake_main_thread);
thread_destroy_event(virge->wake_render_thread);
virge->fifo_thread_run = 0;
thread_set_event(virge->wake_fifo_thread);
thread_wait(virge->fifo_thread);
thread_destroy_event(virge->wake_fifo_thread);
thread_destroy_event(virge->fifo_not_full_event);
svga_close(&virge->svga);
ddc_close(virge->ddc);
@@ -4176,6 +4305,11 @@ static int s3_virge_988_diamond_available(void)
return rom_present(ROM_DIAMOND_STEALTH3D_3000);
}
static int s3_virge_988_stb_available(void)
{
return rom_present(ROM_STB_VELOCITY_3D);
}
static int s3_virge_375_available(void)
{
return rom_present(ROM_VIRGE_DX);
@@ -4302,6 +4436,20 @@ const device_t s3_diamond_stealth_3000_pci_device =
s3_virge_config
};
const device_t s3_stb_velocity_3d_pci_device =
{
"S3 ViRGE/VX (STB Velocity 3D) PCI",
DEVICE_PCI,
S3_STB_VELOCITY_3D,
s3_virge_init,
s3_virge_close,
s3_virge_reset,
{ s3_virge_988_stb_available },
s3_virge_speed_changed,
s3_virge_force_redraw,
s3_virge_config
};
const device_t s3_virge_375_pci_device =
{
"S3 ViRGE/DX (375) PCI",

2
src/video/vid_table.c
View File

@@ -138,6 +138,7 @@ video_cards[] = {
{ "cl_gd5480_pci", &gd5480_pci_device },
{ "ctl3d_banshee_pci", &creative_voodoo_banshee_device },
{ "stealth32_pci", &et4000w32p_pci_device },
{ "spea_mercurylite_pci", &s3_spea_mercury_lite_86c928_pci_device },
{ "stealth64v_pci", &s3_diamond_stealth64_964_pci_device },
{ "elsawin2kprox_964_pci", &s3_elsa_winner2000_pro_x_964_pci_device },
{ "mirocrystal20sv_pci", &s3_mirocrystal_20sv_964_pci_device },
@@ -160,6 +161,7 @@ video_cards[] = {
{ "virge325_pci", &s3_virge_325_pci_device },
{ "stealth3d_2000_pci", &s3_diamond_stealth_2000_pci_device },
{ "stealth3d_3000_pci", &s3_diamond_stealth_3000_pci_device },
{ "stb_velocity3d_pci", &s3_stb_velocity_3d_pci_device },
{ "virge375_pci", &s3_virge_375_pci_device },
{ "stealth3d_2000pro_pci", &s3_diamond_stealth_2000pro_pci_device },
{ "virge385_pci", &s3_virge_385_pci_device },

134
src/video/vid_tvp3026_ramdac.c
View File

@@ -47,6 +47,12 @@ typedef struct
uint8_t misc;
uint8_t type;
uint8_t mode;
uint8_t pll_addr;
uint8_t clock_sel;
struct
{
uint8_t m, n, p;
} pix, mem, loop;
} tvp3026_ramdac_t;
static void
@@ -96,7 +102,6 @@ tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
ramdac->ind_idx = val;
@@ -152,7 +157,7 @@ tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t
svga->dac_hwcursor.xsize = svga->dac_hwcursor.ysize = 64;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.ysize;
svga->dac_hwcursor.ena = ((val & 0x03) != 0);
svga->dac_hwcursor.ena = !!(val & 0x03);
ramdac->mode = val & 0x03;
}
break;
@@ -163,7 +168,7 @@ tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t
svga->dac_hwcursor.xsize = svga->dac_hwcursor.ysize = 64;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.ysize;
svga->dac_hwcursor.ena = ((val & 0x03) != 0);
svga->dac_hwcursor.ena = !!(val & 0x03);
ramdac->mode = val & 0x03;
break;
case 0x0f: /* Latch Control */
@@ -177,6 +182,9 @@ tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t
ramdac->mcr = val;
tvp3026_set_bpp(ramdac, svga);
break;
case 0x1a: /* Clock Selection */
ramdac->clock_sel = val;
break;
case 0x1c: /* Palette-Page Register */
ramdac->ppr = val;
break;
@@ -187,6 +195,51 @@ tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t
ramdac->misc = val;
svga->ramdac_type = (val & 0x08) ? RAMDAC_8BIT : RAMDAC_6BIT;
break;
case 0x2c: /* PLL Address */
ramdac->pll_addr = val;
break;
case 0x2d: /* Pixel clock PLL data */
switch (ramdac->pll_addr & 3) {
case 0:
ramdac->pix.n = val;
break;
case 1:
ramdac->pix.m = val;
break;
case 2:
ramdac->pix.p = val;
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 1) & 3) | (ramdac->pll_addr & 0xfc);
break;
case 0x2e: /* Memory Clock PLL Data */
switch ((ramdac->pll_addr >> 2) & 3) {
case 0:
ramdac->mem.n = val;
break;
case 1:
ramdac->mem.m = val;
break;
case 2:
ramdac->mem.p = val;
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 4) & 0x0c) | (ramdac->pll_addr & 0xf3);
break;
case 0x2f: /* Loop Clock PLL Data */
switch ((ramdac->pll_addr >> 4) & 3) {
case 0:
ramdac->loop.n = val;
break;
case 1:
ramdac->loop.m = val;
break;
case 2:
ramdac->loop.p = val;
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 0x10) & 0x30) | (ramdac->pll_addr & 0xcf);
break;
case 0x39: /* MCLK/Loop Clock Control */
ramdac->mclk = val;
break;
@@ -292,6 +345,9 @@ tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *p, svga_t *svga)
case 0x19: /* Multiplex Control */
temp = ramdac->mcr;
break;
case 0x1a: /* Clock Selection */
temp = ramdac->clock_sel;
break;
case 0x1c: /* Palette-Page Register */
temp = ramdac->ppr;
break;
@@ -301,6 +357,54 @@ tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *p, svga_t *svga)
case 0x1e: /* Miscellaneous Control */
temp = ramdac->misc;
break;
case 0x2c: /* PLL Address */
temp = ramdac->pll_addr;
break;
case 0x2d: /* Pixel clock PLL data */
switch (ramdac->pll_addr & 3) {
case 0:
temp = ramdac->pix.n;
break;
case 1:
temp = ramdac->pix.m;
break;
case 2:
temp = ramdac->pix.p;
break;
case 3:
temp = 0x40; /*PLL locked to frequency*/
break;
}
break;
case 0x2e: /* Memory Clock PLL Data */
switch ((ramdac->pll_addr >> 2) & 3) {
case 0:
temp = ramdac->mem.n;
break;
case 1:
temp = ramdac->mem.m;
break;
case 2:
temp = ramdac->mem.p;
break;
case 3:
temp = 0x40; /*PLL locked to frequency*/
break;
}
break;
case 0x2f: /* Loop Clock PLL Data */
switch ((ramdac->pll_addr >> 4) & 3) {
case 0:
temp = ramdac->loop.n;
break;
case 1:
temp = ramdac->loop.m;
break;
case 2:
temp = ramdac->loop.p;
break;
}
break;
case 0x39: /* MCLK/Loop Clock Control */
temp = ramdac->mclk;
break;
@@ -436,6 +540,29 @@ tvp3026_hwcursor_draw(svga_t *svga, int displine)
}
float
tvp3026_getclock(int clock, void *p)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) p;
int n, m, pl;
float f_vco, f_pll;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
/*Fvco = 8 x Fref x (65 - M) / (65 - N)*/
/*Fpll = Fvco / 2^P*/
n = ramdac->pix.n & 0x3f;
m = ramdac->pix.m & 0x3f;
pl = ramdac->pix.p & 0x03;
f_vco = 8.0 * 14318184 * (float)(65 - m) / (float)(65 - n);
f_pll = f_vco / (float)(1 << pl);
return f_pll;
}
void *
tvp3026_ramdac_init(const device_t *info)
{
@@ -447,6 +574,7 @@ tvp3026_ramdac_init(const device_t *info)
ramdac->latch_cntl = 0x06;
ramdac->true_color = 0x80;
ramdac->mcr = 0x98;
ramdac->clock_sel = 0x07;
ramdac->mclk = 0x18;
return ramdac;

10
src/win/Makefile.mingw
View File

@@ -75,6 +75,9 @@ ifeq ($(DEV_BUILD), y)
ifndef ISAMEM_IAB
ISAMEM_IAB := y
endif
ifndef ISAMEM_BRAT
ISAMEM_BRAT := y
endif
ifndef OLIVETTI
OLIVETTI := y
endif
@@ -130,6 +133,9 @@ else
ifndef ISAMEM_IAB
ISAMEM_IAB := n
endif
ifndef ISAMEM_BRAT
ISAMEM_BRAT := n
endif
ifndef OLIVETTI
OLIVETTI := n
endif
@@ -470,6 +476,10 @@ ifeq ($(ISAMEM_IAB), y)
OPTS += -DUSE_ISAMEM_IAB
endif
ifeq ($(ISAMEM_BRAT), y)
OPTS += -DUSE_ISAMEM_BRAT
endif
ifeq ($(OLIVETTI), y)
OPTS += -DUSE_OLIVETTI
DEVBROBJ += olivetti_eva.o

4
src/win/languages/ru-RU.rc
View File

@@ -37,7 +37,7 @@ BEGIN
MENUITEM "&Изменяемый размер окна", IDM_VID_RESIZE
MENUITEM "&Запомнить размер и положение", IDM_VID_REMEMBER
MENUITEM SEPARATOR
POPUP "&Рендерер"
POPUP "&Рендеринг"
BEGIN
MENUITEM "&SDL (Software)", IDM_VID_SDL_SW
MENUITEM "SDL (&Hardware)", IDM_VID_SDL_HW
@@ -144,7 +144,7 @@ BEGIN
MENUITEM "&Точка останова журнала\tCtrl+F10", IDM_LOG_BREAKPOINT
# endif
# ifdef ENABLE_VRAM_DUMP
MENUITEM "&Выгрузка дампа видео-ОЗУ\tCtrl+F1", IDM_DUMP_VRAM
MENUITEM "&Выгрузка дампа видеопамяти\tCtrl+F1", IDM_DUMP_VRAM
# endif
# endif
END