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Chipsets.

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This commit is contained in:
OBattler
2022-07-16 02:58:37 +02:00
parent d68121ae89
commit f6fef765d7
15 changed files with 15 additions and 15 deletions
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2
src/chipset/ali1489.c
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@@ -318,7 +318,7 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) { if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) {
switch (dev->regs[0x35] & 0x30) { switch (dev->regs[0x35] & 0x30) {
case 0x00: case 0x00:
smi_line = 1; smi_raise();
break; break;
case 0x10: case 0x10:
nmi_raise(); nmi_raise();

2
src/chipset/contaq_82c59x.c
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@@ -242,7 +242,7 @@ contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val; dev->regs[dev->index] = val;
if (val & 0x80) { if (val & 0x80) {
if (dev->regs[0x65] & 0x80) if (dev->regs[0x65] & 0x80)
smi_line = 1; smi_raise();
dev->smi_status[0] |= 0x10; dev->smi_status[0] |= 0x10;
} }
break; break;

2
src/chipset/ims8848.c
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@@ -230,7 +230,7 @@ ims8848_write(uint16_t addr, uint8_t val, void *priv)
if (dev->idx == 0x1b) { if (dev->idx == 0x1b) {
ims8848_smram(dev); ims8848_smram(dev);
if (!(old & 0x10) && (val & 0x10)) if (!(old & 0x10) && (val & 0x10))
smi_line = 1; smi_raise();
} else if (dev->idx == 0x1c) } else if (dev->idx == 0x1c)
pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED); pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
break; break;

2
src/chipset/intel_420ex.c
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@@ -423,7 +423,7 @@ i420ex_fast_off_count(void *priv)
cpu_fast_off_count--; cpu_fast_off_count--;
if (cpu_fast_off_count == 0) { if (cpu_fast_off_count == 0) {
smi_line = 1; smi_raise();
dev->regs[0xaa] |= 0x20; dev->regs[0xaa] |= 0x20;
cpu_fast_off_count = dev->regs[0xa8] + 1; cpu_fast_off_count = dev->regs[0xa8] + 1;
} }

2
src/chipset/intel_piix.c
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@@ -1334,7 +1334,7 @@ piix_fast_off_count(void *priv)
cpu_fast_off_count--; cpu_fast_off_count--;
if (cpu_fast_off_count == 0) { if (cpu_fast_off_count == 0) {
smi_line = 1; smi_raise();
dev->regs[0][0xaa] |= 0x20; dev->regs[0][0xaa] |= 0x20;
cpu_fast_off_count = dev->regs[0][0xa8] + 1; cpu_fast_off_count = dev->regs[0][0xa8] + 1;
} }

2
src/chipset/intel_sio.c
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@@ -432,7 +432,7 @@ sio_fast_off_count(void *priv)
cpu_fast_off_count--; cpu_fast_off_count--;
if (cpu_fast_off_count == 0) { if (cpu_fast_off_count == 0) {
smi_line = 1; smi_raise();
dev->regs[0xaa] |= 0x20; dev->regs[0xaa] |= 0x20;
cpu_fast_off_count = dev->regs[0xa8] + 1; cpu_fast_off_count = dev->regs[0xa8] + 1;
} }

2
src/chipset/opti895.c
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@@ -175,7 +175,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
case 0xe1: case 0xe1:
if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) { if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) {
smi_line = 1; smi_raise();
dev->forced_green = 1; dev->forced_green = 1;
break; break;
} }

2
src/chipset/sis_5511.c
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@@ -225,7 +225,7 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
case 0x60: case 0x60:
dev->pci_conf[addr] = val & 0x3e; dev->pci_conf[addr] = val & 0x3e;
if ((dev->pci_conf[0x68] & 1) && (val & 2)) { if ((dev->pci_conf[0x68] & 1) && (val & 2)) {
smi_line = 1; smi_raise();
dev->pci_conf[0x69] |= 1; dev->pci_conf[0x69] |= 1;
} }
break; break;

2
src/chipset/sis_5571.c
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@@ -288,7 +288,7 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
if ((dev->pci_conf[0x9b] & 1) && !!(val & 2)) if ((dev->pci_conf[0x9b] & 1) && !!(val & 2))
{ {
smi_line = 1; smi_raise();
dev->pci_conf[0x9d] |= 1; dev->pci_conf[0x9d] |= 1;
} }
break; break;

2
src/chipset/sis_85c496.c
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@@ -390,7 +390,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
if (dev->pci_conf[0x80] & 0x10) if (dev->pci_conf[0x80] & 0x10)
picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]); picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]);
else else
smi_line = 1; smi_raise();
smi_block = 1; smi_block = 1;
dev->pci_conf[0xa0] |= 0x10; dev->pci_conf[0xa0] |= 0x10;
} }

2
src/chipset/sis_85c4xx.c
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@@ -104,7 +104,7 @@ sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv)
if (dev->regs[0x18] & 0x02) { if (dev->regs[0x18] & 0x02) {
if (dev->regs[0x0b] & 0x10) if (dev->regs[0x0b] & 0x10)
smi_line = 1; smi_raise();
else else
picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12)); picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12));
soft_reset_mask = 1; soft_reset_mask = 1;

2
src/chipset/sis_85c50x.c
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@@ -176,7 +176,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
case 0x60: /* SMI */ case 0x60: /* SMI */
if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) { if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
dev->pci_conf[0x69] |= 0x01; dev->pci_conf[0x69] |= 0x01;
smi_line = 1; smi_raise();
} }
dev->pci_conf[addr] = val & 0x3e; dev->pci_conf[addr] = val & 0x3e;
break; break;

2
src/chipset/umc_8886.c
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@@ -232,7 +232,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
if (dev->pci_conf_sb[0][0x46] & 0x40) if (dev->pci_conf_sb[0][0x46] & 0x40)
picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10)); picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10));
else else
smi_line = 1; smi_raise();
dev->pci_conf_sb[0][0xa3] |= 0x04; dev->pci_conf_sb[0][0xa3] |= 0x04;
} }

2
src/chipset/via_pipc.c
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@@ -790,7 +790,7 @@ pipc_fm_write(uint16_t addr, uint8_t val, void *priv)
/* Fire NMI/SMI if enabled. */ /* Fire NMI/SMI if enabled. */
if (dev->ac97_regs[0][0x48] & 0x01) { if (dev->ac97_regs[0][0x48] & 0x01) {
if (dev->ac97_regs[0][0x48] & 0x04) if (dev->ac97_regs[0][0x48] & 0x04)
smi_line = 1; smi_raise();
else else
nmi_raise(); nmi_raise();
} }

2
src/chipset/via_vt82c49x.c
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@@ -234,7 +234,7 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
case 0x54: case 0x54:
if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) { if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) {
if (dev->regs[0x5b] & 0x20) if (dev->regs[0x5b] & 0x20)
smi_line = 1; smi_raise();
else else
picint(1 << 15); picint(1 << 15);
dev->regs[0x55] = 0x01; dev->regs[0x55] = 0x01;