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Merge branch 'master' of github.com:86Box/86Box into tc1995

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This commit is contained in:
TC1995
2020-07-07 22:14:49 +02:00
parent bef93a81b3 4bb10138d9
commit fb87236d7d
23 changed files with 1386 additions and 100 deletions
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2
.github/FUNDING.yml vendored Normal file
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@@ -0,0 +1,2 @@
patreon: 86box
custom: ["https://paypal.me/86Box"]

3
README.md
View File

@@ -54,3 +54,6 @@ Donations
---------
We do not charge you for the emulator but donations are still welcome:
https://paypal.me/86Box.
You can now also support the project on Pateron:
https://www.patreon.com/86box.

72
src/chipset/opti283.c
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@@ -35,6 +35,9 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
typedef struct
{
uint8_t index,
@@ -43,54 +46,46 @@ typedef struct
static void opti283_shadow_recalc(opti283_t *dev)
{
uint32_t base;
uint32_t shflags, i = 0;
uint32_t base, i;
uint32_t shflagsc, shflagsd, shflagse, shflagsf;
shadowbios = 0;
shadowbios_write = 0;
shadowbios = !(dev->regs[0x11] & 0x80);
shadowbios_write = (dev->regs[0x11] & 0x80);
if(dev->regs[0x11] & 0x10){
shflagsc = MEM_READ_INTERNAL;
shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagsc = disabled_shadow;
if(dev->regs[0x11] & 0x20){
shflagsd = MEM_READ_INTERNAL;
shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagsd = disabled_shadow;
if(dev->regs[0x11] & 0x40){
shflagse = MEM_READ_INTERNAL;
shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
} else shflagse = disabled_shadow;
/* F0000 - FFFFF segmentation */
if(!(dev->regs[0x11] & 0x80)){
shadowbios = 1;
shadowbios_write = 0;
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
} else {
shadowbios = 0;
shadowbios_write = 1;
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
mem_set_mem_state_both(0xf0000, 0x10000, shflagsf);
/* C0000 - CFFFF segmentation */
for(i = 4; i < 8; i++){
base = 0xc0000 + ((i-4) << 14);
if((dev->regs[0x13] & (1 << i)) & (dev->regs[0x11] & 0x10)){
shflags = MEM_READ_INTERNAL;
shflags |= (!(dev->regs[0x11] & 0x01)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
mem_set_mem_state_both(base, 0x4000, shflags);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
base = 0xc0000 + ((i-4) << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow);
}
/* D0000 - DFFFF segmentation */
for(i = 0; i < 4; i++){
base = 0xd0000 + (i << 14);
if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x20)){
shflags = MEM_READ_INTERNAL;
shflags |= (!(dev->regs[0x11] & 0x02)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
mem_set_mem_state(base, 0x4000, shflags);
} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
base = 0xd0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow);
}
/* E0000 - EFFFF segmentation */
for(i = 4; i < 8; i++){
base = 0xe0000 + ((i-4) << 14);
if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x40)){
shflags = MEM_READ_INTERNAL;
shflags |= (!(dev->regs[0x11] & 0x04)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED;
mem_set_mem_state(base, 0x4000, shflags);
} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
base = 0xe0000 + ((i-4) << 14);
mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow);
}
}
@@ -105,12 +100,13 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
dev->index = val;
break;
case 0x24:
/*pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);*/
/* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */
dev->regs[dev->index] = val;
switch(dev->index){
case 0x10:
cpu_update_waitstates();
break;
case 0x11:
case 0x12:

14
src/chipset/opti495.c
View File

@@ -131,12 +131,13 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
switch (addr) {
case 0x22:
opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val);
dev->idx = val;
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= 0x2c)) {
if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) {
dev->regs[dev->idx] = val;
opti495_log("dev->regs[%04x] = %08x\n", dev->idx, val);
opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val);
switch(dev->idx) {
case 0x21:
@@ -168,9 +169,14 @@ opti495_read(uint16_t addr, void *priv)
opti495_t *dev = (opti495_t *) priv;
switch (addr) {
case 0x22:
opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret);
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= 0x2c))
if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) {
ret = dev->regs[dev->idx];
opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret);
}
break;
case 0xe1:
case 0xe2:
@@ -197,6 +203,8 @@ opti495_init(const device_t *info)
opti495_t *dev = (opti495_t *) malloc(sizeof(opti495_t));
memset(dev, 0, sizeof(opti495_t));
device_add(&port_92_device);
io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);

40
src/chipset/opti5x7.c
View File

@@ -45,35 +45,38 @@ static void
opti5x7_recalc(opti5x7_t *dev)
{
uint32_t base;
uint32_t i, j, shflags = 0;
uint32_t i, shflags = 0;
uint32_t reg, lowest_bit;
uint32_t write = 0;
shadowbios = 0;
shadowbios_write = 0;
for (i = 0; i < 8; i++) {
j = i / 2.01; /*Probably not a great way of doing this, but it does work*/
base = 0xc0000 + (j << 14);
lowest_bit = j * 2;
reg = 0x04 + ((base >> 16) & 0x01);
shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : write;
write = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
mem_set_mem_state(base, 0x4000, shflags);
base = 0xc0000 + (i << 14);
lowest_bit = (i << 1) & 0x07;
reg = 0x04 + ((base >> 16) & 0x01);
shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(base, 0x4000, shflags);
}
shadowbios |= !!(dev->regs[0x06] & 0x05);
shadowbios_write |= !!(dev->regs[0x06] & 0x0a);
shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : write;
write = (dev->regs[0x06] & 0x01) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xe0000, 0x10000, shflags);
shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : write;
write = (dev->regs[0x06] & 0x04) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xf0000, 0x10000, shflags);
flushmmucache();
}
static void
opti5x7_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -90,7 +93,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
case 0x02:
cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08);
break;
case 0x04:
case 0x05:
case 0x06:
@@ -138,9 +141,6 @@ opti5x7_init(const device_t *info)
io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
dev->port_92 = device_add(&port_92_device);
// pclog("OPTi 5x7 init\n");
opti5x7_recalc(dev);
return dev;
}

725
src/chipset/stpc.c Normal file
View File

@@ -0,0 +1,725 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the STPC series of SoCs.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/port_92.h>
#include <86box/usb.h>
#include <86box/chipset.h>
#define STPC_NB_CLIENT 0x01
#define STPC_ISAB_CLIENT 0x02
#define STPC_ISAB_CONSUMER2 0x04
#define STPC_IDE_ATLAS 0x08
#define STPC_USB 0x10
typedef struct stpc_t
{
uint32_t local;
/* Main registers (port 22h/23h) */
uint8_t reg_offset;
uint8_t regs[256];
/* Host bus interface */
uint16_t host_base;
uint8_t host_offset;
uint8_t host_regs[256];
/* Local bus */
uint16_t localbus_base;
uint8_t localbus_offset;
uint8_t localbus_regs[256];
/* PCI devices */
uint8_t pci_conf[4][256];
usb_t *usb;
} stpc_t;
#define ENABLE_STPC_LOG 1
#ifdef ENABLE_STPC_LOG
int stpc_do_log = ENABLE_STPC_LOG;
static void
stpc_log(const char *fmt, ...)
{
va_list ap;
if (stpc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define stpc_log(fmt, ...)
#endif
static void
stpc_recalcmapping(stpc_t *dev)
{
uint8_t reg, bitpair;
uint32_t base, size;
int state;
shadowbios = 0;
shadowbios_write = 0;
for (reg = 0; reg <= 3; reg++) {
for (bitpair = 0; bitpair <= (reg == 3 ? 0 : 3); bitpair++) {
if (reg == 3) {
size = 0x10000;
base = 0xf0000;
} else {
size = 0x4000;
base = 0xc0000 + (size * ((reg * 4) + bitpair));
}
stpc_log("STPC: Shadowing for %05x-%05x (reg %02x bp %d wmask %02x rmask %02x) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
state = 0;
if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
stpc_log(" w on");
state |= MEM_WRITE_INTERNAL;
if (base >= 0xe0000)
shadowbios_write |= 1;
} else {
stpc_log(" w off");
state |= MEM_WRITE_EXTANY;
}
if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
stpc_log("; r on\n");
state |= MEM_READ_INTERNAL;
if (base >= 0xe0000)
shadowbios |= 1;
} else {
stpc_log("; r off\n");
state |= MEM_READ_EXTANY;
}
mem_set_mem_state(base, size, state);
}
}
flushmmucache();
}
static void
stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
static void
stpc_host_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: host_write(%04x, %02x)\n", addr, val);
if (addr == dev->host_base)
dev->host_offset = val;
else if (addr == dev->host_base + 4)
dev->host_regs[dev->host_offset] = val;
}
static uint8_t
stpc_host_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->host_base)
ret = dev->host_offset;
else if (addr == dev->host_base + 4)
ret = dev->host_regs[dev->host_offset];
else
ret = 0xff;
stpc_log("STPC: host_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: localbus_write(%04x, %02x)\n", addr, val);
if (addr == dev->localbus_base)
dev->localbus_offset = val;
else if (addr == dev->localbus_base + 4)
dev->localbus_regs[addr] = val;
}
static uint8_t
stpc_localbus_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->localbus_base)
ret = dev->localbus_offset;
else if (addr == dev->localbus_base + 4)
ret = dev->localbus_regs[dev->localbus_offset];
else
ret = 0xff;
stpc_log("STPC: localbus_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: nb_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x06: case 0x07: case 0x08:
case 0x09: case 0x0a: case 0x0b: case 0x0e:
case 0x51: case 0x53: case 0x54:
return;
case 0x05:
val &= 0x01;
break;
case 0x50:
val &= 0x1f;
break;
case 0x52:
val &= 0x70;
break;
}
dev->pci_conf[0][addr] = val;
}
static uint8_t
stpc_nb_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[0][addr];
stpc_log("STPC: nb_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_ide_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: ide_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x06: case 0x07: case 0x08:
case 0x09: case 0x0a: case 0x0b: case 0x0e:
return;
case 0x05:
val &= 0x01;
break;
}
dev->pci_conf[2][addr] = val;
}
static uint8_t
stpc_ide_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[2][addr];
stpc_log("STPC: ide_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_isab_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) {
stpc_ide_write(0, addr, val, priv);
return;
}
stpc_log("STPC: isab_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x06: case 0x07: case 0x08:
case 0x09: case 0x0a: case 0x0b: case 0x0e:
return;
case 0x05:
val &= 0x01;
break;
}
dev->pci_conf[1][addr] = val;
}
static uint8_t
stpc_isab_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func == 1 && !(dev->local & STPC_IDE_ATLAS))
return stpc_ide_read(0, addr, priv);
else if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[1][addr];
stpc_log("STPC: isab_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_usb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: usb_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x06: case 0x07: case 0x08:
case 0x09: case 0x0a: case 0x0b: case 0x0e:
case 0x10:
return;
case 0x05:
val &= 0x01;
break;
case 0x11:
dev->pci_conf[3][addr] = val & 0xf0;
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
break;
case 0x12: case 0x13:
dev->pci_conf[3][addr] = val;
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
break;
}
dev->pci_conf[3][addr] = val;
}
static uint8_t
stpc_usb_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[3][addr];
stpc_log("STPC: usb_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_remap_host(stpc_t *dev, uint16_t host_base)
{
stpc_log("STPC: Remapping host bus from %04x to %04x\n", dev->host_base, host_base);
io_removehandler(dev->host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
if (host_base) {
io_sethandler(host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
}
dev->host_base = host_base;
}
static void
stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
{
stpc_log("STPC: Remapping local bus from %04x to %04x\n", dev->localbus_base, localbus_base);
io_removehandler(dev->localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
if (localbus_base) {
io_sethandler(localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
}
dev->localbus_base = localbus_base;
}
static void
stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: reg_write(%04x, %02x)\n", addr, val);
if (addr == 0x22) {
dev->reg_offset = val;
} else {
stpc_log("STPC: regs[%02x] = %02x\n", dev->reg_offset, val);
switch (dev->reg_offset) {
case 0x12:
if (dev->regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
else if (dev->regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
break;
case 0x13:
if (dev->regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
else if (dev->regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
break;
case 0x21:
val &= 0xfe;
break;
case 0x22:
val &= 0x7f;
break;
case 0x25: case 0x26: case 0x27: case 0x28:
if (dev->reg_offset == 0x28) {
val &= 0xe3;
stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
}
dev->regs[dev->reg_offset] = val;
stpc_recalcmapping(dev);
break;
case 0x29:
val &= 0x0f;
break;
case 0x36:
val &= 0x3f;
break;
}
dev->regs[dev->reg_offset] = val;
}
}
static uint8_t
stpc_reg_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == 0x22)
ret = dev->reg_offset;
else if (dev->reg_offset >= 0xc0)
return 0xff; /* Cyrix CPU registers: let the CPU code handle those */
else
ret = dev->regs[dev->reg_offset];
stpc_log("STPC: reg_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_reset(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: reset()\n");
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x7b] = 0xff;
io_removehandler(0x22, 2,
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
io_sethandler(0x22, 2,
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
}
static void
stpc_setup(stpc_t *dev)
{
stpc_log("STPC: setup()\n");
/* Northbridge */
dev->pci_conf[0][0x00] = 0x4a;
dev->pci_conf[0][0x01] = 0x10;
if (dev->local & STPC_NB_CLIENT) {
dev->pci_conf[0][0x02] = 0x64;
dev->pci_conf[0][0x03] = 0x05;
} else {
dev->pci_conf[0][0x02] = 0x0a;
dev->pci_conf[0][0x03] = 0x02;
}
dev->pci_conf[0][0x04] = 0x07;
dev->pci_conf[0][0x06] = 0x80;
dev->pci_conf[0][0x07] = 0x02;
dev->pci_conf[0][0x0b] = 0x06;
/* ISA Bridge */
dev->pci_conf[1][0x00] = 0x4a;
dev->pci_conf[1][0x01] = 0x10;
if (dev->local & STPC_ISAB_CLIENT) {
dev->pci_conf[1][0x02] = 0xcc;
dev->pci_conf[1][0x03] = 0x55;
} else if (dev->local & STPC_ISAB_CONSUMER2) {
dev->pci_conf[1][0x02] = 0x0b;
dev->pci_conf[1][0x03] = 0x02;
} else {
dev->pci_conf[1][0x02] = 0x10;
dev->pci_conf[1][0x03] = 0x02;
}
dev->pci_conf[1][0x04] = 0x0f;
dev->pci_conf[1][0x06] = 0x80;
dev->pci_conf[1][0x07] = 0x02;
dev->pci_conf[1][0x0a] = 0x01;
dev->pci_conf[1][0x0b] = 0x06;
dev->pci_conf[1][0x0e] = 0x40;
/* IDE */
dev->pci_conf[2][0x00] = 0x4a;
dev->pci_conf[2][0x01] = 0x10;
if (dev->local & STPC_IDE_ATLAS) {
dev->pci_conf[2][0x02] = 0x28;
dev->pci_conf[2][0x03] = 0x02;
} else {
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
}
dev->pci_conf[2][0x06] = 0x80;
dev->pci_conf[2][0x07] = 0x02;
dev->pci_conf[2][0x09] = 0x8a;
dev->pci_conf[2][0x0a] = 0x01;
dev->pci_conf[2][0x0b] = 0x01;
dev->pci_conf[2][0x0e] = 0x40;
dev->pci_conf[2][0x10] = 0x01;
dev->pci_conf[2][0x14] = 0x01;
dev->pci_conf[2][0x18] = 0x01;
dev->pci_conf[2][0x1c] = 0x01;
dev->pci_conf[2][0x40] = 0x60;
dev->pci_conf[2][0x41] = 0x97;
dev->pci_conf[2][0x42] = 0x60;
dev->pci_conf[2][0x43] = 0x97;
dev->pci_conf[2][0x44] = 0x60;
dev->pci_conf[2][0x45] = 0x97;
dev->pci_conf[2][0x46] = 0x60;
dev->pci_conf[2][0x47] = 0x97;
/* USB */
if (dev->usb) {
dev->pci_conf[3][0x00] = 0x4a;
dev->pci_conf[3][0x01] = 0x10;
dev->pci_conf[3][0x02] = 0x30;
dev->pci_conf[3][0x03] = 0x02;
dev->pci_conf[3][0x06] = 0x80;
dev->pci_conf[3][0x07] = 0x02;
dev->pci_conf[3][0x09] = 0x10;
dev->pci_conf[3][0x0a] = 0x03;
dev->pci_conf[3][0x0b] = 0x0c;
dev->pci_conf[3][0x0e] = 0x40;
}
}
static void
stpc_close(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: close()\n");
free(dev);
}
static void *
stpc_init(const device_t *info)
{
stpc_log("STPC: init()\n");
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
memset(dev, 0, sizeof(stpc_t));
dev->local = info->local;
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
if (dev->local & STPC_IDE_ATLAS)
pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
if (dev->local & STPC_USB) {
dev->usb = device_add(&usb_device);
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
}
stpc_setup(dev);
stpc_reset(dev);
smram[0].host_base = 0x000a0000;
smram[0].ram_base = 0x000a0000;
smram[0].size = 0x00020000;
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
stpc_smram_map(0, smram[0].host_base, smram[0].size, 0);
stpc_smram_map(1, smram[0].host_base, smram[0].size, 1);
device_add(&port_92_pci_device);
return dev;
}
const device_t stpc_client_device =
{
"STPC Client",
DEVICE_PCI,
STPC_NB_CLIENT | STPC_ISAB_CLIENT,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t stpc_consumer2_device =
{
"STPC Consumer-II",
DEVICE_PCI,
STPC_ISAB_CONSUMER2,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t stpc_elite_device =
{
"STPC Elite",
DEVICE_PCI,
0,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t stpc_atlas_device =
{
"STPC Atlas",
DEVICE_PCI,
STPC_IDE_ATLAS | STPC_USB,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};

8
src/codegen_new/codegen_backend_x86.c
View File

@@ -304,12 +304,20 @@ void codegen_backend_init()
block_write_data = NULL;
cpu_state.old_fp_control = 0;
#ifndef _MSC_VER
asm(
"fstcw %0\n"
"stmxcsr %1\n"
: "=m" (cpu_state.old_fp_control2),
"=m" (cpu_state.old_fp_control)
);
#else
__asm
{
fstcw cpu_state.old_fp_control2
stmxcsr cpu_state.old_fp_control
}
#endif
cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
}

9
src/cpu/cpu.c
View File

@@ -399,10 +399,10 @@ cpu_set(void)
hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
#else
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
#endif
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx486DX4 || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
#else
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx486DX4 || cpu_s->cpu_type == CPU_Cx5x86);
#endif
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC );
cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP);
@@ -935,6 +935,7 @@ cpu_set(void)
case CPU_Cx486S:
case CPU_Cx486DX:
case CPU_Cx486DX2:
case CPU_Cx486DX4:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else

18
src/cpu/cpu.h
View File

@@ -132,15 +132,19 @@ extern CPU cpus_Am386SX[];
extern CPU cpus_Am386DX[];
extern CPU cpus_486SLC[];
extern CPU cpus_486DLC[];
extern CPU cpus_IBM386SLC[];
extern CPU cpus_IBM486SLC[];
extern CPU cpus_IBM486BL[];
extern CPU cpus_i486S1[];
extern CPU cpus_IBM386SLC[];
extern CPU cpus_IBM486SLC[];
extern CPU cpus_IBM486BL[];
extern CPU cpus_i486S1[];
extern CPU cpus_Am486S1[];
extern CPU cpus_Cx486S1[];
extern CPU cpus_i486[];
extern CPU cpus_Am486[];
extern CPU cpus_Cx486[];
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern CPU cpus_STPC6675[];
extern CPU cpus_STPC133[];
#endif
extern CPU cpus_WinChip[];
extern CPU cpus_WinChip_SS7[];
extern CPU cpus_Pentium5V[];
@@ -156,10 +160,8 @@ extern CPU cpus_K56_SS7[];
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern CPU cpus_6x863V[];
extern CPU cpus_6x86[];
#ifdef USE_NEW_DYNAREC
extern CPU cpus_6x86SS7[];
#endif
#endif
extern CPU cpus_Cyrix3[];
extern CPU cpus_PentiumPro[];
extern CPU cpus_PentiumII66[];
@@ -293,10 +295,10 @@ typedef struct {
#ifdef USE_NEW_DYNAREC
uint32_t old_fp_control, new_fp_control;
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
uint16_t old_fp_control2, new_fp_control2;
#endif
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
uint32_t trunc_fp_control;
#endif
#endif

14
src/cpu/cpu_table.c
View File

@@ -366,6 +366,20 @@ CPU cpus_Cx486[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#if defined(DEV_BRANCH) && defined(USE_STPC)
/* All STPC timings and Cyrix CPUID values assumed. */
CPU cpus_STPC6675[] = {
{"STPC 66", CPU_Cx486DX, fpus_internal, 66666666, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"STPC 75", CPU_Cx486DX, fpus_internal, 75000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_STPC133[] = {
{"STPC 133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
CPU cpus_6x863V[] = {
/*Cyrix 6x86*/

322
src/disk/hdc_ide_opti611.c Normal file
View File

@@ -0,0 +1,322 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C611/611A VLB IDE controller.
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
typedef struct
{
uint8_t tries,
in_cfg, cfg_locked,
regs[19];
} opti611_t;
static void opti611_ide_handler(opti611_t *dev);
static void
opti611_cfg_write(uint16_t addr, uint8_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
addr &= 0x0007;
switch (addr) {
case 0x0000:
case 0x0001:
dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr] = val;
break;
case 0x0002:
dev->regs[0x12] = (val & 0xc1) | 0x02;
if (val & 0xc0) {
dev->in_cfg = 0;
opti611_ide_handler(dev);
}
if (val & 0x40)
dev->cfg_locked = 1;
break;
case 0x0003:
dev->regs[0x03] = (val & 0xdf);
break;
case 0x0005:
dev->regs[0x05] = (dev->regs[0x05] & 0x78) | (val & 0x87);
break;
case 0x0006:
dev->regs[0x06] = val;
break;
}
}
static void
opti611_cfg_writew(uint16_t addr, uint16_t val, void *priv)
{
opti611_cfg_write(addr, val & 0xff, priv);
opti611_cfg_write(addr + 1, val >> 8, priv);
}
static void
opti611_cfg_writel(uint16_t addr, uint32_t val, void *priv)
{
opti611_cfg_writew(addr, val & 0xffff, priv);
opti611_cfg_writew(addr + 2, val >> 16, priv);
}
static uint8_t
opti611_cfg_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti611_t *dev = (opti611_t *) priv;
addr &= 0x0007;
switch (addr) {
case 0x0000:
case 0x0001:
ret = dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr];
break;
case 0x0002:
ret = ((!!in_smm) << 7);
if (ret & 0x80)
ret |= (dev->regs[addr] & 0x7f);
break;
case 0x0003: case 0x0004: case 0x0005: case 0x0006:
ret = dev->regs[addr];
break;
}
return ret;
}
static uint16_t
opti611_cfg_readw(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = opti611_cfg_read(addr, priv);
ret |= (opti611_cfg_read(addr + 1, priv) << 8);
return ret;
}
static uint32_t
opti611_cfg_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = opti611_cfg_readw(addr, priv);
ret |= (opti611_cfg_readw(addr + 2, priv) << 16);
return ret;
}
static void
opti611_ide_write(uint16_t addr, uint8_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0003);
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = val;
}
}
static void
opti611_ide_writew(uint16_t addr, uint16_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0002) | 0x0001;
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
}
static void
opti611_ide_writel(uint16_t addr, uint32_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | 0x0003;
dev->regs[0x04] = 0x00;
}
}
static uint8_t
opti611_ide_read(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0003);
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
return 0xff;
}
static uint16_t
opti611_ide_readw(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0002) | 0x0001;
if ((addr & 0x0007) == 0x0001) {
dev->tries = (dev->tries + 1) & 0x01;
if ((dev->tries == 0x00) && !dev->cfg_locked) {
dev->in_cfg = 1;
opti611_ide_handler(dev);
}
}
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
return 0xffff;
}
static uint32_t
opti611_ide_readl(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
if (dev->regs[0x03] & 0x02) {
smi_line = 1;
dev->regs[0x02] = smia9 | smia2 | 0x0003;
dev->regs[0x04] = 0x00;
}
return 0xffffffff;
}
static void
opti611_ide_handler(opti611_t *dev)
{
ide_pri_disable();
io_removehandler(0x01f0, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
io_removehandler(0x01f0, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
if (dev->in_cfg && !dev->cfg_locked) {
io_sethandler(0x01f0, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
} else {
if (dev->regs[0x03] & 0x01)
ide_pri_enable();
io_sethandler(0x01f0, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
}
}
static void
opti611_close(void *priv)
{
opti611_t *dev = (opti611_t *) priv;
free(dev);
}
static void *
opti611_init(const device_t *info)
{
opti611_t *dev = (opti611_t *) malloc(sizeof(opti611_t));
memset(dev, 0, sizeof(opti611_t));
dev->regs[0x12] = 0x80;
dev->regs[0x03] = 0x01;
dev->regs[0x05] = 0x20;
device_add(&ide_vlb_device);
opti611_ide_handler(dev);
return dev;
}
const device_t ide_opti611_vlb_device = {
"OPTi 82C611/82C611A VLB",
0,
0,
opti611_init, opti611_close, NULL,
NULL, NULL, NULL,
NULL
};

8
src/include/86box/chipset.h
View File

@@ -84,6 +84,14 @@ extern const device_t sis_85c496_ls486e_device;
extern const device_t sis_85c50x_device;
#endif
/* ST */
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern const device_t stpc_client_device;
extern const device_t stpc_consumer2_device;
extern const device_t stpc_elite_device;
extern const device_t stpc_atlas_device;
#endif
/* VIA */
extern const device_t via_vpx_device;
extern const device_t via_vp3_device;

6
src/include/86box/hdc.h
View File

@@ -13,8 +13,8 @@
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2016-2019 Miran Grca.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2020 Miran Grca.
* Copyright 2017-2020 Fred N. van Kempen.
*/
#ifndef EMU_HDC_H
# define EMU_HDC_H
@@ -50,6 +50,8 @@ extern const device_t ide_vlb_2ch_device; /* vlb_ide_2ch */
extern const device_t ide_pci_device; /* pci_ide */
extern const device_t ide_pci_2ch_device; /* pci_ide_2ch */
extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */
extern const device_t ide_ter_device;
extern const device_t ide_qua_device;

6
src/include/86box/machine.h
View File

@@ -282,6 +282,12 @@ extern int machine_at_4dps_init(const machine_t *);
extern int machine_at_alfredo_init(const machine_t *);
extern int machine_at_486sp3g_init(const machine_t *);
extern int machine_at_486ap4_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern int machine_at_itoxstar_init(const machine_t *);
extern int machine_at_arb1479_init(const machine_t *);
extern int machine_at_pcm9340_init(const machine_t *);
extern int machine_at_pcm5330_init(const machine_t *);
#endif
#ifdef EMU_DEVICE_H
extern const device_t *at_acera1g_get_device(void);

2
src/include/86box/sio.h
View File

@@ -40,8 +40,10 @@ extern const device_t w83877f_president_device;
extern const device_t w83877tf_device;
extern const device_t w83877tf_acorp_device;
extern const device_t w83977f_device;
extern const device_t w83977f_370_device;
extern const device_t w83977tf_device;
extern const device_t w83977ef_device;
extern const device_t w83977ef_370_device;
#endif /*EMU_SIO_H*/

136
src/machine/m_at_386dx_486.c
View File

@@ -40,6 +40,7 @@
#include <86box/video.h>
#include <86box/flash.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/hwm.h>
#include <86box/machine.h>
int
@@ -610,3 +611,138 @@ machine_at_486ap4_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_STPC)
int
machine_at_itoxstar_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/itoxstar/stara.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_client_device);
device_add(&ide_vlb_device);
device_add(&sst_flash_29ee020_device);
hwm_values_t machine_hwm = {
{ /* fan speeds (incorrect divisor for some reason) */
3000, /* Chassis */
3000 /* CPU */
}, { /* temperatures */
30, /* Chassis */
30 /* CPU */
}, { /* voltages */
0, /* unused */
0, /* unused */
3300, /* Vio */
RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */
RESISTOR_DIVIDER(5000, 1, 2) /* -5V (divider values bruteforced) */
}
};
hwm_set_values(machine_hwm);
device_add(&w83781d_device);
return ret;
}
int
machine_at_arb1479_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/arb1479/1479a.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 0, 0, 0);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_consumer2_device);
device_add(&ide_vlb_2ch_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pcm9340_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pcm9340/9340v110.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_elite_device);
device_add(&ide_vlb_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pcm5330_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pcm5330/5330_13b.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&w83977f_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_atlas_device);
device_add(&ide_vlb_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
#endif

10
src/machine/m_at_socket4_5.c
View File

@@ -53,8 +53,8 @@ machine_at_excalibur_init(const machine_t *model)
machine_at_common_init(model);
device_add(&ide_vlb_device);
device_add(&opti5x7_device);
device_add(&ide_opti611_vlb_device);
device_add(&fdc37c661_device);
device_add(&keyboard_at_ami_device);
@@ -182,10 +182,10 @@ machine_at_opti560l_init(const machine_t *model)
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&intel_flash_bxt_device);
return ret;
}
@@ -213,10 +213,10 @@ machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&intel_flash_bxt_device);
return ret;
}

28
src/machine/machine_table.c
View File

@@ -171,8 +171,8 @@ const machine_t machines[] = {
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL },
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[OPTi 291] DTK Award 386SX", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_awardsx_init, NULL },
/* 386SX machines which utilize the MCA bus */
@@ -195,14 +195,14 @@ const machine_t machines[] = {
{ "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
/* 486 machines with just the ISA slot */
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
/* 486 machines */
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL },
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL },
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_vli486sv2g_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ami471_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_WIN471)
@@ -210,10 +210,10 @@ const machine_t machines[] = {
#endif
{ "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_dtk486_init, NULL },
{ "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_ali1429_init, NULL },
{ "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_winbios1429_init, NULL },
{ "[VLSI 82c480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
{ "[VLSI 82C480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
/* 486 machines with utilize the MCA bus */
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
@@ -227,6 +227,12 @@ const machine_t machines[] = {
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_ls486e_init, NULL },
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_r418_init, NULL },
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_4dps_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_STPC)
{ "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, {{"ST", cpus_STPC6675}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_itoxstar_init, NULL },
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 160, 8, 255, machine_at_arb1479_init, NULL },
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 32, 0, 255, machine_at_pcm9340_init, NULL },
{ "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 64, 64, 0, 255, machine_at_pcm5330_init, NULL },
#endif
/* Socket 4 machines */
/* OPTi 596/597 */
@@ -238,11 +244,11 @@ const machine_t machines[] = {
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL },
#endif
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL },
{ "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VPP60)
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
#endif
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
/* Socket 5 machines */

1
src/sio/sio_fdc37c661.c
View File

@@ -161,7 +161,6 @@ fdc37c661_write(uint16_t port, uint8_t val, void *priv)
case 0:
if (valxor & 0x10)
fdc_handler(dev);
break;
case 1:
if (valxor & 3)

26
src/sio/sio_w83977f.c
View File

@@ -43,7 +43,7 @@ typedef struct {
dev_regs[256][208];
int locked, rw_locked,
cur_reg, base_address,
type;
type, hefras;
fdc_t *fdc;
serial_t *uart[2];
} w83977f_t;
@@ -351,6 +351,7 @@ w83977f_reset(w83977f_t *dev)
}
dev->regs[0x22] = 0xff;
dev->regs[0x24] = dev->type ? 0x84 : 0xa4;
dev->regs[0x26] = dev->hefras;
/* WARNING: Array elements are register - 0x30. */
/* Logical Device 0 (FDC) */
@@ -492,7 +493,8 @@ w83977f_init(const device_t *info)
w83977f_t *dev = (w83977f_t *) malloc(sizeof(w83977f_t));
memset(dev, 0, sizeof(w83977f_t));
dev->type = info->local;
dev->type = info->local & 0x0f;
dev->hefras = info->local & 0x40;
dev->fdc = device_add(&fdc_at_smc_device);
@@ -515,6 +517,16 @@ const device_t w83977f_device = {
};
const device_t w83977f_370_device = {
"Winbond W83977F Super I/O (Port 370h)",
0,
0x40,
w83977f_init, w83977f_close, NULL,
NULL, NULL, NULL,
NULL
};
const device_t w83977tf_device = {
"Winbond W83977TF Super I/O",
0,
@@ -533,3 +545,13 @@ const device_t w83977ef_device = {
NULL, NULL, NULL,
NULL
};
const device_t w83977ef_370_device = {
"Winbond W83977TF Super I/O (Port 370h)",
0,
0x42,
w83977f_init, w83977f_close, NULL,
NULL, NULL, NULL,
NULL
};

9
src/video/vid_paradise.c
View File

@@ -122,6 +122,7 @@ void paradise_out(uint16_t addr, uint8_t val, void *p)
{
svga->gdcreg[0xe] = val;
paradise_remap(paradise);
svga_recalctimings(svga);
return;
}
break;
@@ -251,9 +252,11 @@ void paradise_recalctimings(svga_t *svga)
if (paradise->type == WD90C30)
svga->interlace = (svga->crtc[0x2d] & 0x20);
svga->lowres = !(svga->gdcreg[0xe] & 0x01);
if (svga->bpp == 8 && !svga->lowres)
if (svga->gdcreg[0xe] & 0x01) {
svga->bpp = 8;
svga->lowres = 0;
svga->render = svga_render_8bpp_highres;
}
}
static void paradise_write(uint32_t addr, uint8_t val, void *p)
@@ -299,7 +302,7 @@ void *paradise_init(const device_t *info, uint32_t memsize)
switch(info->local) {
case PVGA1A:
svga_init(info, &paradise->svga, paradise, memsize, /*256kb*/
NULL,
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);

25
src/win/Makefile.mingw
View File

@@ -42,6 +42,9 @@ ifeq ($(DEV_BUILD), y)
ifndef CL5422
CL5422 := y
endif
ifndef CYRIX_6X86
CYRIX_6X86 := y
endif
ifndef LASERXT
LASERXT := y
endif
@@ -69,6 +72,9 @@ ifeq ($(DEV_BUILD), y)
ifndef SIEMENS
SIEMENS := y
endif
ifndef STPC
STPC := y
endif
ifndef VGAWONDER
VGAWONDER := y
endif
@@ -106,6 +112,9 @@ else
ifndef CL5422
CL5422 := n
endif
ifndef CYRIX_6X86
CYRIX_6X86 := n
endif
ifndef LASERXT
LASERXT := n
endif
@@ -133,6 +142,9 @@ else
ifndef SIEMENS
SIEMENS := n
endif
ifndef STPC
STPC := y
endif
ifndef VGAWONDER
VGAWONDER := n
endif
@@ -473,6 +485,10 @@ ifeq ($(CL5422), y)
OPTS += -DUSE_CL5422
endif
ifeq ($(CYRIX_6X86), y)
OPTS += -DUSE_CYRIX_6X86
endif
ifeq ($(LASERXT), y)
OPTS += -DUSE_LASERXT
DEVBROBJ += m_xt_laserxt.o
@@ -512,6 +528,11 @@ ifeq ($(SIEMENS), y)
OPTS += -DUSE_SIEMENS
endif
ifeq ($(STPC), y)
OPTS += -DUSE_STPC
STPCOBJ := stpc.o
endif
ifeq ($(596B), y)
OPTS += -DUSE_596B
endif
@@ -572,7 +593,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o i82335.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o \
sis_85c310.o sis_85c471.o sis_85c496.o opti283.o opti291.o \
sis_85c310.o sis_85c471.o sis_85c496.o opti283.o opti291.o $(STPCOBJ) \
via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o vl82c480.o \
amd640.o
@@ -626,7 +647,7 @@ HDDOBJ := hdd.o \
hdc_xta.o \
hdc_esdi_at.o hdc_esdi_mca.o \
hdc_xtide.o hdc_ide.o \
hdc_ide_sff8038i.o
hdc_ide_opti611.o hdc_ide_sff8038i.o
CDROMOBJ := cdrom.o \
cdrom_image_backend.o cdrom_image.o

2
src/win/win_settings.c
View File

@@ -627,7 +627,7 @@ win_settings_machine_recalc_cpu_m(HWND hdlg)
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)lptsTemp);
c++;
}
EnableWindow(h, TRUE);
EnableWindow(h, (c == 1) ? FALSE : TRUE);
if (temp_cpu >= c)
temp_cpu = (c - 1);
SendMessage(h, CB_SETCURSEL, temp_cpu, 0);